cpu: microcode: Use microcode stored in binary format

Using a copiler to compile something that's already a binary is pretty stupid. Now that Stefan converted most microcode in blobs to a plain binary, use the binary version. Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 22:38:06 -07:00
parent b20a600ba7
commit 1d85700503
71 changed files with 51 additions and 451 deletions
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
 cbfs_include_ucode = y
 endif

-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
-	@printf "    LD         $(subst $(obj)/,,$(@))\n"
-	$(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
-	$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+	@echo $(cpu_microcode_bins)
+	cat $+ > $@

 cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
 cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
 ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ b/src/cpu/amd/model_10xxx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ b/src/cpu/intel/ep80579/microcode_blob.c
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff70000

-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
-	default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
 endif
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c

 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	/* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	/* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
-	#include <microcode-m12306a2_00000008.h>
-	#include <microcode-m12306a4_00000007.h>
-	#include <microcode-m12306a5_00000007.h>
-	#include <microcode-m12306a8_00000010.h>
-	#include <microcode-m12306a9_00000019.h>
-#endif
--- a/src/cpu/intel/fsp_model_206ax/microcode_size.h
+++ b/src/cpu/intel/fsp_model_206ax/microcode_size.h
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
-	#define MICROCODE_REGION_LENGTH 0xC000
-#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
-	#define MICROCODE_REGION_LENGTH 0x2800
-#endif
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
 	default 0xfff60040

-config MICROCODE_INCLUDE_PATH
-	string "Location of the intel microcode patches"
-	default "../intel/cpu/rangeley/microcode"
-
 endif #CPU_INTEL_FSP_MODEL_406DX
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name

 ramstage-y += acpi.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-		/* Size is 0x14400 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-		/* Size is 0x14800 - update in microcode_size.h when the file changes */
-		#include <microcode-m01406d811d.h>
-#endif
-};
--- a/src/cpu/intel/fsp_model_406dx/microcode_size.h
+++ b/src/cpu/intel/fsp_model_406dx/microcode_size.h
@@ -1,7 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
-	#define MICROCODE_REGION_LENGTH 0x14400
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
-	#define MICROCODE_REGION_LENGTH 0x14800
-#endif
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c

 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ b/src/cpu/intel/haswell/microcode_blob.c
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	/*
-	 * FIXME: Can we just include both microcodes regardless, or is there
-	 * a very good reason why we only use one at a time?
-	 */
-	#if CONFIG_INTEL_LYNXPOINT_LP
-	#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
-	#else
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
-	#endif
-};
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_1067x_init.c
 subdirs-y += ../../x86/name

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ b/src/cpu/intel/model_1067x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name

 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ b/src/cpu/intel/model_106cx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c

 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin

 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ b/src/cpu/intel/model_2065x/microcode_blob.c
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c

 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin

 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
-	#include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@

 ramstage-y += model_65x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ b/src/cpu/intel/model_65x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@

 ramstage-y += model_67x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ b/src/cpu/intel/model_67x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ b/src/cpu/intel/model_68x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_69x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ b/src/cpu/intel/model_69x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ b/src/cpu/intel/model_6bx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6dx_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ b/src/cpu/intel/model_6dx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ b/src/cpu/intel/model_6ex/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ b/src/cpu/intel/model_6fx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ b/src/cpu/intel/model_6xx/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f0x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ b/src/cpu/intel/model_f0x/microcode_blob.c
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f1x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ b/src/cpu/intel/model_f1x/microcode_blob.c
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f2x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ b/src/cpu/intel/model_f2x/microcode_blob.c
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f3x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ b/src/cpu/intel/model_f3x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_f4x_init.c

-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ b/src/cpu/intel/model_f4x/microcode_blob.c
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
-	#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
 ramstage-y += nano_init.c
 ramstage-y += update_ucode.c

-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin

 cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc