soc/intel/tigerlake: Add PCH-H PMC GPE group definitions

Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6
This commit is contained in:
Jeremy Soller
2021-06-17 13:35:39 -06:00
committed by Tim Crawford
parent cca90d8090
commit 1e605551e8

View File

@@ -131,6 +131,22 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4*(x))
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
#define PMC_GPD 0x0
#define PMC_GPP_A 0x1
#define PMC_GPP_R 0x2
#define PMC_GPP_B 0x3
#define PMC_GPP_D 0x4
#define PMC_GPP_C 0x5
#define PMC_GPP_S 0x6
#define PMC_GPP_G 0x7
#define PMC_GPP_E 0x9
#define PMC_GPP_F 0xA
#define PMC_GPP_H 0xB
#define PMC_GPP_J 0xC
#define PMC_GPP_K 0xD
#define PMC_GPP_I 0xE
#else
#define PMC_GPP_B 0x0
#define PMC_GPP_T 0x1
#define PMC_GPP_A 0x2
@@ -143,6 +159,7 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define PMC_GPP_F 0xA
#define PMC_GPP_C 0xB
#define PMC_GPP_E 0xC
#endif
#define GBLRST_CAUSE0 0x1924
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)