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src/*/post_code.h: Change post code prefix to POSTCODE

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The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
	src/include/cpu/intel/post_codes.h \
	src/soc/intel/common/block/include/intelblocks/post_codes.h"

array=`grep -r "#define POST_" $header | \
	tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`

for str in $array; do
	splitstr=`echo $str | cut -d '_' -f2-`
	grep -r $str src | cut -d ':' -f 1 | \
		xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done

Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Yuchen He
2023-07-25 21:28:36 +02:00
committed by Matt DeVillier
parent 71b8ee0da4
commit 1e67adbc73
23 changed files with 159 additions and 159 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/stoneyridge/bootblock.c
View File

@@ -77,7 +77,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
void bootblock_soc_early_init(void)
{
bootblock_fch_early_init();
post_code(POST_BOOTBLOCK_SOC_EARLY_INIT);
post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT);
}
void bootblock_soc_init(void)

6
src/soc/amd/stoneyridge/chip.c
View File

@@ -108,15 +108,15 @@ struct chip_operations soc_amd_stoneyridge_ops = {
static void earliest_ramstage(void *unused)
{
if (!acpi_is_wakeup_s3()) {
post_code(POST_PSP_LOAD_SMU);
post_code(POSTCODE_PSP_LOAD_SMU);
if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
post_code(POST_AGESA_AMDINITENV);
post_code(POSTCODE_AGESA_AMDINITENV);
do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
} else {
/* Complete the initial system restoration */
post_code(POST_AGESA_AMDS3LATERESTORE);
post_code(POSTCODE_AGESA_AMDS3LATERESTORE);
do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
}
}

18
src/soc/amd/stoneyridge/romstage.c
View File

@@ -37,10 +37,10 @@ void __weak mainboard_romstage_entry(void)
static void agesa_call(void)
{
post_code(POST_AGESA_AMDINITRESET);
post_code(POSTCODE_AGESA_AMDINITRESET);
do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
post_code(POST_AGESA_AMDINITEARLY);
post_code(POSTCODE_AGESA_AMDINITEARLY);
/* APs will not exit amdinitearly */
do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
}
@@ -68,10 +68,10 @@ void __noreturn romstage_main(void)
bsp_agesa_call();
if (!s3_resume) {
post_code(POST_AGESA_AMDINITPOST);
post_code(POSTCODE_AGESA_AMDINITPOST);
do_agesawrapper(AMD_INIT_POST, "amdinitpost");
post_code(POST_AGESA_AMDINITPOST_DONE);
post_code(POSTCODE_AGESA_AMDINITPOST_DONE);
/*
* TODO: This is a hack to work around current AGESA behavior.
* AGESA needs to change to reflect that coreboot owns
@@ -101,16 +101,16 @@ void __noreturn romstage_main(void)
wrmsr(SYSCFG_MSR, sys_cfg);
} else {
printk(BIOS_INFO, "S3 detected\n");
post_code(POST_AGESA_AMDINITRESUME);
post_code(POSTCODE_AGESA_AMDINITRESUME);
do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
post_code(POST_AGESA_AMDINITRESUME_DONE);
post_code(POSTCODE_AGESA_AMDINITRESUME_DONE);
}
post_code(POST_PSP_NOTIFY_DRAM);
post_code(POSTCODE_PSP_NOTIFY_DRAM);
psp_notify_dram();
post_code(POST_PSP_NOTIFY_DRAM_DONE);
post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE);
if (cbmem_recovery(s3_resume))
printk(BIOS_CRIT, "Failed to recover cbmem\n");
if (romstage_handoff_init(s3_resume))
@@ -119,7 +119,7 @@ void __noreturn romstage_main(void)
if (CONFIG(SMM_TSEG))
smm_list_regions();
post_code(POST_ROMSTAGE_RUN_POSTCAR);
post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR);
prepare_and_run_postcar();
}