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mb/system76/rpl: oryp11: Fix CNVi

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According to the schematics:

- PCH_LAN_WAKE# is not connected
- M.2_BT_PCMIN is not connected

Addtionally, leave both CLKREQ and RST# for CNVi as FSP configured.

Change-Id: I6f249ca778ad741469475b02163a2eee2e7626de
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-15 15:22:18 -07:00
committed by Jeremy Soller
parent ff7cd52733
commit 1e97c67c46
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/system76/rpl/variants/oryp11/gpio.c
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@@ -7,7 +7,7 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW_N
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_GPO(GPD2, 0, DEEP), // PCH_LAKE_WAKE#
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
@@ -94,9 +94,9 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D2, NONE),
PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
PAD_NC(GPP_D4, NONE),
PAD_CFG_GPO(GPP_D5, 0, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
PAD_CFG_GPO(GPP_D6, 0, DEEP), // M.2_BT_PCMOUT_CLKREQ0
PAD_CFG_GPO(GPP_D7, 0, DEEP), // M.2_BT_PCMIN
// GPP_D5 (M.2_BT_PCMFRM_CRF_RST_N) configured by FSP
// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
PAD_NC(GPP_D7, NONE), // M.2_BT_PCMIN
PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),