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soc/amd/sabrina/include/iomap: update MMIO device mappings

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Compared to Cezanne there are 3 more UARTs with DMA controllers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2022-01-11 16:42:42 +01:00
parent 9d93b16487
commit 1f0eb6b0db
1 changed files with 6 additions and 2 deletions
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8
src/soc/amd/sabrina/include/soc/iomap.h
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@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */
#ifndef AMD_SABRINA_IOMAP_H
#define AMD_SABRINA_IOMAP_H
@ -34,6 +32,12 @@
#define APU_DMAC1_BASE 0xfedc8000
#define APU_UART0_BASE 0xfedc9000
#define APU_UART1_BASE 0xfedca000
#define APU_DMAC2_BASE 0xfedcc000
#define APU_DMAC3_BASE 0xfedcd000
#define APU_UART2_BASE 0xfedce000
#define APU_UART3_BASE 0xfedcf000
#define APU_DMAC4_BASE 0xfedd0000
#define APU_UART4_BASE 0xfedd1000
#define APU_EMMC_BASE 0xfedd5000
#define APU_EMMC_CONFIG_BASE 0xfedd5800