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mainboard/intel/galileo: Enable SPI controllers

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Enable the SPI controllers on the Quark SoC.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Load the SPI driver stack
*  Testing is successful when the time is able to be displayed on a
   set of seven-segment displays controlled by a Maxim MAX6950 SPI
   display controller.

Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14109
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-03-03 15:30:48 -08:00 committed by Martin Roth
parent 66a98ee967
commit 1f1f2c4d38
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/galileo/devicetree.cb
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@ -37,8 +37,8 @@ chip soc/intel/quark
device pci 14.5 on end # 8086 0936 - HSUART 1
device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
device pci 15.0 off end # 8086 0935 - SPI controller 0
device pci 15.1 off end # 8086 0935 - SPI controller 1
device pci 15.0 on end # 8086 0935 - SPI controller 0
device pci 15.1 on end # 8086 0935 - SPI controller 1
device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1