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mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

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GL9763e doesn’t support L0s state, so disable L0s at the root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
This commit is contained in:
Kevin Chang 2022-03-22 11:22:02 +08:00 committed by Tim Wawrzynczak
parent 6e52c1da4a
commit 1f54599b98
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -407,6 +407,7 @@ chip soc/intel/alderlake
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"