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drivers/fsp1_1: fix VBT Loading by using GMA common function

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Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.

As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.

Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.

Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier
2018-06-20 00:35:27 -05:00
committed by Patrick Georgi
parent 95278a59bd
commit 1f6e3294f8
3 changed files with 12 additions and 243 deletions
Download Patch File Download Diff File Expand all files Collapse all files

178
src/drivers/intel/fsp1_1/include/fsp/gma.h
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@@ -1,178 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Chromium OS Authors
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _GMA_H_
#define _GMA_H_
#include <types.h>
#include <compiler.h>
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
#define SWSCI 0xe8 /* SWSCI Register */
#define GSSCIE (1 << 0) /* SCI Event trigger */
#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
/* mailbox 0: header */
typedef struct {
u8 signature[16];
u32 size;
u32 version;
u8 sbios_version[32];
u8 vbios_version[16];
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
#define IGD_MBOX1 (1 << 0)
#define IGD_MBOX2 (1 << 1)
#define IGD_MBOX3 (1 << 2)
#define IGD_MBOX4 (1 << 3)
#define IGD_MBOX5 (1 << 4)
#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
IGD_MBOX4 | IGD_MBOX5)
#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
#define SBIOS_VERSION_SIZE 32
/* mailbox 1: public ACPI methods */
typedef struct {
u32 drdy;
u32 csts;
u32 cevt;
u8 reserved1[20];
u32 didl[8];
u32 cpdl[8];
u32 cadl[8];
u32 nadl[8];
u32 aslp;
u32 tidx;
u32 chpd;
u32 clid;
u32 cdck;
u32 sxsw;
u32 evts;
u32 cnot;
u32 nrdy;
u8 reserved2[60];
} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
u32 scic;
u32 parm;
u32 dslp;
u8 reserved[244];
} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
u32 ardy;
u32 aslc;
u32 tche;
u32 alsi;
u32 bclp;
u32 pfit;
u32 cblv;
u16 bclm[20];
u32 cpfm;
u32 epfm;
u8 plut[74];
u32 pfmb;
u32 ccdv;
u32 pcft;
u8 reserved[94];
} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
#define IGD_FIELD_VALID (1 << 31)
#define IGD_WORD_FIELD_VALID (1 << 15)
#define IGD_PFIT_STRETCH 6
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
opregion_header_t header;
opregion_mailbox1_t mailbox1;
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
} __packed igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
} __packed optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
#endif /* _GMA_H_ */

23
src/drivers/intel/fsp1_1/include/fsp/gop.h
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@@ -1,23 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _FSP1_1_GOP_H_
#define _FSP1_1_GOP_H_
#include <fsp/gma.h>
const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
#endif /* _FSP1_1_GOP_H_ */

54
src/drivers/intel/fsp1_1/vbt.c
View File

@@ -17,47 +17,10 @@
#include <bootmode.h>
#include <cbfs.h>
#include <console/console.h>
#include <fsp/gop.h>
#include <drivers/intel/gma/opregion.h>
#include <fsp/ramstage.h>
#include <fsp/util.h>
/* Reading VBT table from flash */
const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
{
size_t vbt_size;
union {
const optionrom_vbt_t *data;
uint32_t *signature;
} vbt;
/* Locate the vbt file in cbfs */
vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size);
if (!vbt.data) {
printk(BIOS_INFO,
"FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
return NULL;
}
/* Validate the vbt file */
if (*vbt.signature != VBT_SIGNATURE) {
printk(BIOS_WARNING,
"FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
return NULL;
}
*vbt_len = vbt_size;
printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
vbt.data, *vbt_len);
#if IS_ENABLED(CONFIG_DISPLAY_VBT)
/* Display the vbt file contents */
printk(BIOS_DEBUG, "VBT Data:\n");
hexdump(vbt.data, *vbt_len);
printk(BIOS_DEBUG, "\n");
#endif
/* Return the pointer to the vbt file data */
return vbt.data;
}
#include <lib.h>
/* Locate VBT and pass it to FSP GOP */
void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
@@ -70,11 +33,18 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
} else if (display_init_required()) {
/* Get VBT data */
vbt_data = fsp_get_vbt(&vbt_len);
if (vbt_data != NULL)
vbt_data = locate_vbt(&vbt_len);
if (vbt_data != NULL) {
if (IS_ENABLED(CONFIG_DISPLAY_VBT)) {
/* Display the vbt file contents */
printk(BIOS_DEBUG, "VBT Data:\n");
hexdump(vbt_data, vbt_len);
printk(BIOS_DEBUG, "\n");
}
printk(BIOS_DEBUG, "Passing VBT to GOP\n");
else
} else {
printk(BIOS_DEBUG, "VBT not found!\n");
}
} else {
printk(BIOS_DEBUG, "Not passing VBT to GOP\n");
}