AMD-8111: Add TINY_BOOTBLOCK support.
Also, add missing license header to amd8111_enable_rom.c, add some more code comments and use PCI IDs from pci_ids.h instead of hardcoding. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
@@ -85,7 +85,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#define RC0 ((1<<0)<<8)
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@@ -126,7 +125,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -89,7 +89,6 @@ static int spd_read_byte(u32 device, u32 address)
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#include "cpu/amd/microcode/microcode.c"
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#include "cpu/amd/model_10xxx/update_microcode.c"
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#include "cpu/amd/model_10xxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdfam10/early_ht.c"
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static const u8 spd_addr[] = {
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@@ -197,9 +196,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* mov bsp to bus 0xff when > 8 nodes */
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set_bsp_node_CHtExtNodeCfgEn();
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enumerate_ht_chain();
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/* Setup the rom access for 4M */
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amd8111_enable_rom();
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}
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post_code(0x30);
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@@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -88,7 +87,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -88,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include <spd.h>
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#define RC0 ((1<<1)<<8) // Not sure about these values
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@@ -115,7 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -97,7 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -97,7 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -73,7 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -96,7 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -73,7 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -97,7 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -73,7 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -97,7 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -91,7 +90,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -82,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -93,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -93,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -80,7 +79,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -93,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@@ -80,7 +79,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include <spd.h>
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#define RC0 ((1<<2)<<8)
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@@ -140,7 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -86,7 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include <spd.h>
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#define RC0 ((1<<2)<<8)
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@@ -119,7 +118,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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amd8111_enable_rom();
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}
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if (bist == 0)
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@@ -20,8 +20,9 @@
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config SOUTHBRIDGE_AMD_AMD8111
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bool
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select IOAPIC
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select TINY_BOOTBLOCK
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/amd/amd8111/bootblock.c"
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depends on SOUTHBRIDGE_AMD_AMD8111
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string
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default "southbridge/amd/amd8111/bootblock.c"
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depends on SOUTHBRIDGE_AMD_AMD8111
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@@ -1,15 +1,42 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_ids.h>
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/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
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static void amd8111_enable_rom(void)
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{
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unsigned char byte;
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u8 byte;
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device_t dev;
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/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
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/* Locate the amd8111 */
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dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
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dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_8111_ISA), 0);
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/* Set the 5MB enable bits */
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/* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
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/* Set the 5MB enable bits. */
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byte = pci_io_read_config8(dev, 0x43);
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byte |= 0xC0;
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byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
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byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
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pci_io_write_config8(dev, 0x43, byte);
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}
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@@ -1,6 +1,6 @@
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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static void bootblock_southbridge_init(void) {
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/* Setup the rom access for 4M */
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static void bootblock_southbridge_init(void)
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{
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amd8111_enable_rom();
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}
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Reference in New Issue
Block a user