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AMD-8111: Add TINY_BOOTBLOCK support.

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Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-11-26 22:35:11 +00:00
parent df323fcefd
commit 1f7d3c5672
21 changed files with 39 additions and 49 deletions
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7
src/southbridge/amd/amd8111/Kconfig
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@@ -20,8 +20,9 @@
config SOUTHBRIDGE_AMD_AMD8111
bool
select IOAPIC
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/amd8111/bootblock.c"
depends on SOUTHBRIDGE_AMD_AMD8111
string
default "southbridge/amd/amd8111/bootblock.c"
depends on SOUTHBRIDGE_AMD_AMD8111

39
src/southbridge/amd/amd8111/amd8111_enable_rom.c
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@@ -1,15 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Linux Networx
* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
static void amd8111_enable_rom(void)
{
unsigned char byte;
u8 byte;
device_t dev;
/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
/* Locate the amd8111 */
dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_8111_ISA), 0);
/* Set the 5MB enable bits */
/* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
/* Set the 5MB enable bits. */
byte = pci_io_read_config8(dev, 0x43);
byte |= 0xC0;
byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
pci_io_write_config8(dev, 0x43, byte);
}

4
src/southbridge/amd/amd8111/bootblock.c
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@@ -1,6 +1,6 @@
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
static void bootblock_southbridge_init(void) {
/* Setup the rom access for 4M */
static void bootblock_southbridge_init(void)
{
amd8111_enable_rom();
}