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soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable

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As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.

However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.

Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.

Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2024-04-28 21:34:20 +02:00 committed by Felix Held
parent 0b90b0fb05
commit 1fa0fcbd7b
4 changed files with 31 additions and 10 deletions
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2
src/soc/intel/cannonlake/Kconfig
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@ -64,7 +64,7 @@ config SOC_INTEL_CANNONLAKE_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS

14
src/soc/intel/common/block/graphics/Kconfig
View File

@ -8,10 +8,20 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS
if SOC_INTEL_COMMON_BLOCK_GRAPHICS
config SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
bool
help
Selected by platforms that require DDI-A bifurcation setup.
Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP
bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP)
and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if
applicable.
config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION
bool
depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
help
Selected by mainboards that use DDI-E, which is most commonly
used to drive a DP-to-VGA adapter to provide a VGA connector.
config SOC_INTEL_DISABLE_IGD
bool "Disable Integrated GFX Controller (0:2:0)"

23
src/soc/intel/common/block/graphics/graphics.c
View File

@ -124,6 +124,21 @@ int fsp_soc_report_external_display(void)
return graphics_get_framebuffer_address() && get_external_display_status();
}
static void configure_ddi_a_bifurcation(void)
{
u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
/* Only program if the buffer is not enabled yet. */
if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE)
return;
if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION))
ddi_buf_ctl &= ~DDI_A_4_LANES;
else
ddi_buf_ctl |= DDI_A_4_LANES;
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
static void gma_init(struct device *const dev)
{
intel_gma_init_igd_opregion();
@ -135,12 +150,8 @@ static void gma_init(struct device *const dev)
if (!CONFIG(RUN_FSP_GOP))
graphics_soc_panel_init(dev);
if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) {
const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
/* Only program if the buffer is not enabled yet. */
if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE))
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES);
}
if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3())
configure_ddi_a_bifurcation();
/*
* GFX PEIM module inside FSP binary is taking care of graphics

2
src/soc/intel/skylake/Kconfig
View File

@ -62,7 +62,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER