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mb/system76/oryp5: Fix dGPU init

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Declare dGPU pins in bootblock instead of ramstage as this conflicts
with the driver init.

Change-Id: I9464be9cbd25809367a112ea007c9e84ad8dfc55
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-09 12:47:09 -06:00
committed by Tim Crawford
parent 9eb65f388b
commit 1ffa727cfa
2 changed files with 4 additions and 2 deletions
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4
src/mainboard/system76/oryp5/gpio.c
View File

@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
/* ------- GPIO Group GPP_G ------- */
PAD_NC(GPP_G0, NONE),

2
src/mainboard/system76/oryp5/gpio_early.c
View File

@ -6,6 +6,8 @@
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
};
void mainboard_configure_early_gpios(void)