arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG

Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.

The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.

Add constants for this new CSR.

Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Ronald G Minnich 2024-03-15 21:56:20 -07:00 committed by ron minnich
parent 87fa1d07b5
commit 200f7b7ee1
4 changed files with 22 additions and 0 deletions

View File

@ -110,4 +110,13 @@ config RISCV_USE_ARCH_TIMER
config RISCV_WORKING_HARTID
int
# Newer SoC have the menvconfig register.
# Very few SOC do not have this.
# Older SoC, such as the SiFive FU[57]40, that
# do not have this register, should set this
# to n.
config RISCV_SOC_HAS_MENVCFG
bool
default y
endif # if ARCH_RISCV

View File

@ -800,6 +800,8 @@
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
#define CSR_MENVCFG 0x30a
#define CSR_MENVCFGH 0x31a
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
@ -1292,6 +1294,8 @@ DECLARE_CSR(mideleg, CSR_MIDELEG)
DECLARE_CSR(mie, CSR_MIE)
DECLARE_CSR(mtvec, CSR_MTVEC)
DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
DECLARE_CSR(menvcfg, CSR_MENVCFG)
DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)

View File

@ -48,4 +48,9 @@ config OPENSBI_PLATFORM
config OPENSBI_TEXT_START
hex
default 0x80000000
config RISCV_SOC_HAS_MENVCFG
bool
default n
endif

View File

@ -60,4 +60,8 @@ config OPENSBI_FW_DYNAMIC_BOOT_HART
Choose the first U74 core as boot hart since
hart 0 is the S7 which does not support Supervisor mode
config RISCV_SOC_HAS_MENVCFG
bool
default n
endif