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devicetrees: Remove trailing backslash from multiline values

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It's not needed to put a backslash at the end of a line for quoted
multiline values. Thus, remove it.

Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Felix Singer
2023-10-23 07:26:28 +02:00
committed by Felix Held
parent a41abea65d
commit 21b5a9aff4
34 changed files with 483 additions and 483 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/asrock/h110m/devicetree.cb
View File

@@ -112,11 +112,11 @@ chip soc/intel/skylake
# make boards with better PCHs, which can have up to six SATA ports.
# However, the H110 PCH only has four SATA ports, which explains why
# two connectors are missing.
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
}"
end
device pci 19.0 off end # UART #2

122
src/mainboard/facebook/monolith/devicetree.cb
View File

@@ -38,15 +38,15 @@ chip soc/intel/skylake
register "SaGv" = "SaGv_Enabled"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 0, \
[2] = 0, \
[3] = 0, \
[4] = 0, \
[5] = 0, \
[6] = 0, \
[7] = 0, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 0,
[2] = 0,
[3] = 0,
[4] = 0,
[5] = 0,
[6] = 0,
[7] = 0,
}"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
@@ -77,55 +77,55 @@ chip soc/intel/skylake
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(5.1), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(5.1),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(32), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(32),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(35),\
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(31), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520
}"
# Send an extra VR mailbox command for the PS4 exit issue
@@ -198,18 +198,18 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoDisabled,
}"
device cpu_cluster 0 on end

12
src/mainboard/google/brya/variants/aurash/overridetree.cb
View File

@@ -37,13 +37,13 @@ chip soc/intel/alderlake
}" # Type-A port A2
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(6) | \
USB_PORT_WAKE_ENABLE(7) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(6) |
USB_PORT_WAKE_ENABLE(7) |
USB_PORT_WAKE_ENABLE(8)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
register "tcc_offset" = "0" # TCC of 100C
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{

14
src/mainboard/google/brya/variants/kinox/overridetree.cb
View File

@@ -45,14 +45,14 @@ chip soc/intel/alderlake
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(6) | \
USB_PORT_WAKE_ENABLE(7) | \
USB_PORT_WAKE_ENABLE(8) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(6) |
USB_PORT_WAKE_ENABLE(7) |
USB_PORT_WAKE_ENABLE(8) |
USB_PORT_WAKE_ENABLE(9)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB

12
src/mainboard/google/brya/variants/moli/overridetree.cb
View File

@@ -38,13 +38,13 @@ chip soc/intel/alderlake
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(6) | \
USB_PORT_WAKE_ENABLE(7) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(6) |
USB_PORT_WAKE_ENABLE(7) |
USB_PORT_WAKE_ENABLE(8)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
register "tcc_offset" = "0" # TCC of 100C

12
src/mainboard/google/dedede/variants/boxy/overridetree.cb
View File

@@ -83,13 +83,13 @@ chip soc/intel/jasperlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
#Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
device domain 0 on

20
src/mainboard/google/dedede/variants/dexi/overridetree.cb
View File

@@ -124,17 +124,17 @@ chip soc/intel/jasperlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(7)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
device domain 0 on

20
src/mainboard/google/dedede/variants/taranza/overridetree.cb
View File

@@ -124,17 +124,17 @@ chip soc/intel/jasperlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(7)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
device domain 0 on

16
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@@ -33,15 +33,15 @@ chip soc/intel/skylake
#+----------------+-------+-----------------------------------+
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# GPE configuration

2
src/mainboard/google/kahlee/variants/baseboard/devicetree.cb
View File

@@ -10,7 +10,7 @@ chip soc/amd/stoneyridge
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device domain 0 on

16
src/mainboard/google/puff/variants/ambassador/overridetree.cb
View File

@@ -86,15 +86,15 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

4
src/mainboard/google/puff/variants/dooly/overridetree.cb
View File

@@ -79,9 +79,9 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(3)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/duffy/overridetree.cb
View File

@@ -147,15 +147,15 @@ chip soc/intel/cannonlake
}" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/faffy/overridetree.cb
View File

@@ -155,15 +155,15 @@ chip soc/intel/cannonlake
}" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/genesis/overridetree.cb
View File

@@ -79,15 +79,15 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View File

@@ -147,15 +147,15 @@ chip soc/intel/cannonlake
}" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View File

@@ -79,15 +79,15 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

12
src/mainboard/google/puff/variants/noibat/overridetree.cb
View File

@@ -72,13 +72,13 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/puff/overridetree.cb
View File

@@ -80,15 +80,15 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

16
src/mainboard/google/puff/variants/scout/overridetree.cb
View File

@@ -86,15 +86,15 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(5) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
# Enable eMMC HS400

12
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View File

@@ -83,13 +83,13 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(6)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(5)"
# Enable eMMC HS400

14
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@@ -131,13 +131,13 @@ chip soc/intel/cannonlake
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[6]" = "{
.enable = 1, \
.ocpin = OC_SKIP, \
.tx_bias = USB2_BIAS_0MV, \
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
.pre_emp_bias = USB2_BIAS_28P15MV, \
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
}" # WWAN
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth

80
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@@ -55,55 +55,55 @@ chip soc/intel/skylake
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(4), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(7), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(34), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(35),\
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(35), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520
}"
# Send an extra VR mailbox command for the PS4 exit issue

42
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@@ -73,28 +73,28 @@ chip soc/intel/skylake
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 60W

44
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@@ -24,16 +24,16 @@ chip soc/intel/skylake
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = VR_CFG_AMP(7), \
.voltage_limit = 1520 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520
}"
# Enable Root ports.
@@ -96,18 +96,18 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoPci, \
[PchSerialIoIndexI2C3] = PchSerialIoPci, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
device domain 0 on

104
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@@ -29,55 +29,55 @@ chip soc/intel/skylake
#* VrVoltageLimit command not sent.
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0 ,\
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
# Enable Root ports.
@@ -133,18 +133,18 @@ chip soc/intel/skylake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# Use default SD card detect GPIO configuration

122
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@@ -26,55 +26,55 @@ chip soc/intel/skylake
#* VrVoltageLimit command not sent.
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(4), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0 ,\
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
.voltage_limit = 0
}"
# Enable Root port.
@@ -124,30 +124,30 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 25W

24
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@@ -132,18 +132,18 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 25W

42
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@@ -157,28 +157,28 @@ chip soc/intel/skylake
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoPci, \
[PchSerialIoIndexI2C3] = PchSerialIoPci, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoPci, \
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
[PchSerialIoIndexSpi1] = PchSerialIoPci, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoPci, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoPci,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 25W

10
src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
View File

@@ -89,11 +89,11 @@ chip soc/intel/apollolake
end # LPC
device pci 1f.1 on # SMBUS
chip drivers/i2c/nct7802y # Hardware Monitor
register "sensors" = "{ \
.local_enable = 1, \
.rtd[2] = RTD_VOLTAGE_MODE, \
.rtd[1] = RTD_VOLTAGE_MODE, \
.rtd[0] = RTD_THERMISTOR_MODE, \
register "sensors" = "{
.local_enable = 1,
.rtd[2] = RTD_VOLTAGE_MODE,
.rtd[1] = RTD_VOLTAGE_MODE,
.rtd[0] = RTD_THERMISTOR_MODE,
}"
# FAN0
register "fan[0].mode" = "FAN_SMART"

22
src/mainboard/protectli/vault_cml/devicetree.cb
View File

@@ -89,19 +89,19 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
# USB related
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
USB_PORT_WAKE_ENABLE(4) | \
USB_PORT_WAKE_ENABLE(5) | \
USB_PORT_WAKE_ENABLE(6) | \
USB_PORT_WAKE_ENABLE(7) | \
USB_PORT_WAKE_ENABLE(8) | \
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6) |
USB_PORT_WAKE_ENABLE(7) |
USB_PORT_WAKE_ENABLE(8) |
USB_PORT_WAKE_ENABLE(9)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
USB_PORT_WAKE_ENABLE(2) | \
USB_PORT_WAKE_ENABLE(3) | \
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4)"
register "PchUsb2PhySusPgDisable" = "1"

24
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@@ -175,18 +175,18 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoDisabled,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoDisabled,
}"
device cpu_cluster 0 on end

24
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@@ -152,18 +152,18 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoDisabled,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoDisabled,
}"
device cpu_cluster 0 on end

18
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@@ -5,15 +5,15 @@ chip soc/intel/skylake
# SATA configuration
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 1, \
[5] = 1, \
[6] = 1, \
[7] = 1, \
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
# LPC