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soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init

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The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.

Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.

BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration

Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla 2021-06-10 22:25:48 +05:30 committed by Felix Held
parent 9f91ced9dd
commit 248dbe0908
1 changed files with 4 additions and 10 deletions
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14
src/soc/intel/alderlake/romstage/romstage.c
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@ -129,6 +129,9 @@ void mainboard_romstage_entry(void)
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake)
cse_fw_sync();
/*
* Set low maximum temp threshold value used for dynamic thermal sensor
* shutdown consideration.
@ -140,15 +143,6 @@ void mainboard_romstage_entry(void)
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake) {
/*
* cse_fw_sync() must be called after DRAM initialization as
* HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
* is expected to be executed after DRAM initialization.
*/
if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
cse_fw_sync();
if (!s3wake)
save_dimm_info();
}
}