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soc/marvell/bg4cd: remove cosmos mainboard and bg4cd soc

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The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.

Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19823
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin
2017-05-22 16:28:46 -05:00
committed by Furquan Shaikh
parent 0fb6568444
commit 250715eb2f
27 changed files with 0 additions and 798 deletions
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56
src/mainboard/google/cosmos/Kconfig
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@@ -1,56 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_GOOGLE_COSMOS
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_2048
select COMMON_CBFS_SPI_WRAPPER
select HAVE_HARD_RESET
select MAINBOARD_HAS_CHROMEOS
select SOC_MARVELL_BG4CD
select SPI_FLASH
select SPI_FLASH_SPANSION
config VBOOT
select VBOOT_VBNV_FLASH
config MAINBOARD_DIR
string
default google/cosmos
config MAINBOARD_PART_NUMBER
string
default "Cosmos"
config MAINBOARD_VENDOR
string
default "Google"
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 2
config DRAM_SIZE_MB
int
default 1024
config GBB_HWID
string
depends on CHROMEOS
default "Cosmos TEST 1"
endif # BOARD_GOOGLE_COSMOS

2
src/mainboard/google/cosmos/Kconfig.name
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@@ -1,2 +0,0 @@
config BOARD_GOOGLE_COSMOS
bool "Cosmos"

37
src/mainboard/google/cosmos/Makefile.inc
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@@ -1,37 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
bootblock-y += bootblock.c
bootblock-y += boardid.c
bootblock-y += chromeos.c
bootblock-y += reset.c
verstage-y += boardid.c
verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += boardid.c
romstage-y += chromeos.c
romstage-y += romstage.c
romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/cosmos/board_info.txt
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@@ -1,5 +0,0 @@
Vendor name: Google
Board name: Cosmos Marvell BG4CD reference board
Category: eval
ROM protocol: SPI
ROM socketed: n

21
src/mainboard/google/cosmos/boardid.c
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@@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boardid.h>
uint8_t board_id(void)
{
return -1;
}

20
src/mainboard/google/cosmos/bootblock.c
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@@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
void bootblock_mainboard_init(void)
{
}

31
src/mainboard/google/cosmos/chromeos.c
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@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
}
int get_recovery_mode_switch(void)
{
return 0;
}
int get_write_protect_state(void)
{
return 0;
}

28
src/mainboard/google/cosmos/chromeos.fmd
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@@ -1,28 +0,0 @@
FLASH@0x0 0x200000 {
WP_RO@0x0 0x100000 {
RO_SECTION@0x0 0xf0000 {
BOOTBLOCK@0 128K
COREBOOT(CBFS)@0x20000 0x60000
FMAP@0x80000 0x1000
GBB@0x81000 0x6ef00
RO_FRID@0xeff00 0x100
}
RO_VPD@0xf0000 0x10000
}
RW_SECTION_A@0x100000 0x68000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x65f00
RW_FWID_A@0x67f00 0x100
}
RW_SHARED@0x168000 0x4000 {
SHARED_DATA@0x0 0x4000
}
RW_ELOG@0x16c000 0x4000
RW_SECTION_B@0x180000 0x68000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x65f00
RW_FWID_B@0x67f00 0x100
}
RW_VPD@0x1e8000 0x8000
RW_NVRAM@0x1f0000 0x10000
}

19
src/mainboard/google/cosmos/devicetree.cb
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@@ -1,19 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# TODO fill with Versatile Express board data in QEMU.
chip soc/marvell/bg4cd
device cpu_cluster 0 on end
end

34
src/mainboard/google/cosmos/mainboard.c
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@@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <boot/coreboot_tables.h>
static void mainboard_init(device_t dev)
{
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
}

14
src/mainboard/google/cosmos/memlayout.ld
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@@ -1,14 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/memlayout.ld>

22
src/mainboard/google/cosmos/reset.c
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@@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <reset.h>
void hard_reset(void)
{
while (1)
;
}

53
src/mainboard/google/cosmos/romstage.c
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@@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/stages.h>
#include <armv7.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
#include <soc/sdram.h>
#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "timer.h"
void main(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init();
timestamp_add_now(TS_AFTER_INITRAM);
mmu_init();
mmu_config_range(0, 4096, DCACHE_OFF);
dcache_mmu_enable();
cbmem_initialize_empty();
run_ramstage();
}

34
src/soc/marvell/bg4cd/Kconfig
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@@ -1,34 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOC_MARVELL_BG4CD
bool
default n
select ARCH_BOOTBLOCK_ARMV7_M
select BOOTBLOCK_CUSTOM if VBOOT
select ARCH_RAMSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_VERSTAGE_ARMV7_M
select BOOTBLOCK_CONSOLE
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select GENERIC_GPIO_LIB
if SOC_MARVELL_BG4CD
config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
endif

49
src/soc/marvell/bg4cd/Makefile.inc
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@@ -1,49 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ifeq ($(CONFIG_SOC_MARVELL_BG4CD),y)
bootblock-$(CONFIG_VBOOT) += bootblock_asm.S
bootblock-$(CONFIG_VBOOT) += bootblock.c
bootblock-y += cbmem.c
bootblock-y += i2c.c
bootblock-y += monotonic_timer.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
verstage-y += i2c.c
verstage-y += monotonic_timer.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += romstage.S
romstage-y += cbmem.c
romstage-y += i2c.c
romstage-y += monotonic_timer.c
romstage-y += sdram.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += cbmem.c
ramstage-y += i2c.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
@mv $< $@
endif

26
src/soc/marvell/bg4cd/bootblock.c
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@@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <program_loading.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
void main(void)
{
console_init();
timestamp_init(timestamp_get());
run_romstage();
}

54
src/soc/marvell/bg4cd/bootblock_asm.S
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@@ -1,54 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <arch/asm.h>
ENTRY(_start)
/*
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
add r0, #4
cmp r0, r1
bne init_stack_loop
call_verstage:
ldr sp, =_estack /* Set up stack pointer */
/*
* we don't bl here to preserve lr so that we can return to the caller
* of the bootblock
*/
b main
ENDPROC(_start)

22
src/soc/marvell/bg4cd/cbmem.c
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@@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stddef.h>
void *cbmem_top(void)
{
return NULL;
}

26
src/soc/marvell/bg4cd/i2c.c
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@@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/i2c.h>
#include <soc/i2c.h>
int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count)
{
return 0;
}
void i2c_init(unsigned int bus, unsigned int hz)
{
}

21
src/soc/marvell/bg4cd/include/soc/gpio.h
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@@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_MARVELL_BG4CD_GPIO_H__
#define __SOC_MARVELL_BG4CD_GPIO_H__
#include <types.h>
typedef u32 gpio_t;
#endif /* __SOC_MARVELL_BG4CD_GPIO_H__ */

21
src/soc/marvell/bg4cd/include/soc/i2c.h
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@@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_MARVELL_BG4CD_I2C_H__
#define __SOC_MARVELL_BG4CD_I2C_H__
void i2c_init(unsigned int bus, unsigned int hz);
#endif

40
src/soc/marvell/bg4cd/include/soc/memlayout.ld
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@@ -1,40 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
SRAM_START(0x20000)
BOOTBLOCK(0x20000, 40K)
/* there is no VERSTAGE because it's built into bootblock */
PRERAM_CBFS_CACHE(0x2A000, 8K)
STACK(0x2C000, 8K)
VBOOT2_WORK(0x2E000, 16K)
SRAM_END(0x40000)
DRAM_START(0x40000)
RAMSTAGE(0x40000, 128K)
POSTRAM_CBFS_CACHE(0x60000, 1M)
ROMSTAGE(0xF7A40000, 32K)
TTB(0xF7A48000, 16K)
}

20
src/soc/marvell/bg4cd/include/soc/sdram.h
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@@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__
#define __SOC_MARVELL_BG4CD_SDRAM_H__
void sdram_init(void);
#endif

21
src/soc/marvell/bg4cd/monotonic_timer.c
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@@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <timer.h>
void timer_monotonic_get(struct mono_time *mt)
{
}

79
src/soc/marvell/bg4cd/romstage.S
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@@ -1,79 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <arch/asm.h>
.arm
ENTRY(stage_entry)
/*
* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.
*/
msr cpsr_cxf, #0xdf
bl _thumb_start
ENDPROC(stage_entry)
.thumb
ENTRY(_thumb_start)
bl arm_init_caches
/*
* From Cortex-A Series Programmer's Guide:
* Only CPU 0 performs initialization. Other CPUs go into WFI
* to do this, first work out which CPU this is
* this code typically is run before any other initialization step
*/
mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
and r1, r1, #0x3 @ Extract CPU ID bits
cmp r1, #0
bne wait_for_interrupt @ If this is not core0, wait
/*
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
add r0, #4
cmp r0, r1
bne init_stack_loop
ldr sp, =_estack /* Set up stack pointer */
bl main
wait_for_interrupt:
wfi
mov pc, lr @ back to my caller
ENDPROC(_thumb_start)

22
src/soc/marvell/bg4cd/sdram.c
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@@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <soc/sdram.h>
void sdram_init(void)
{
printk(BIOS_INFO, "Starting SDRAM initialization...\n");
printk(BIOS_INFO, "Finish SDRAM initialization...\n");
}

21
src/soc/marvell/bg4cd/spi.c
View File

@@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <spi-generic.h>
int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
{
return -1;
}