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lemp9: enable s0ix and c6dram

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This commit is contained in:
Jeremy Soller
2020-06-04 08:40:35 -06:00
parent 7f40e1b1f7
commit 27753e2b4f
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/system76/lemp9/devicetree.cb
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@@ -13,8 +13,8 @@ chip soc/intel/cannonlake
register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c)
# Disable s0ix
register "s0ix_enable" = "0"
# Enable s0ix
register "s0ix_enable" = "1"
# PM Timer Enabled
register "PmTimerDisabled" = "0"
@@ -37,7 +37,7 @@ chip soc/intel/cannonlake
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
#register "enable_c6dram" = "1"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
@@ -184,9 +184,9 @@ chip soc/intel/cannonlake
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_WAKE_PIN"
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "0"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration