mb/system76: gpio: Make comments inline

Change-Id: I6f5008d19ebb9976310df80e6eb35b9600085b19
This commit is contained in:
Tim Crawford
2021-03-29 14:09:56 -06:00
committed by Jeremy Soller
parent 844b15fa94
commit 292e37c4dc
7 changed files with 1516 additions and 3650 deletions

View File

@ -10,521 +10,219 @@
/* Early pad configuration in romstage. */ /* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_NC(GPP_C22, NONE), // NC
// UART2_TXD PAD_NC(GPP_C23, NONE), // NC
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management PAD_NC(GPD0, NONE), // PM_BATLOW#
// PM_BATLOW# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_NC(GPD0, NONE), PAD_NC(GPD2, NONE), // NC
// AC_PRESENT PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
// NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD2, NONE), PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
// PWR_BTN# PAD_NC(GPD7, NONE), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
// SUSB#_PCH PAD_NC(GPD9, NONE), // GPD9_RTD3
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
// SUSC#_PCH PAD_NC(GPD11, NONE), // NC
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// SLP_A#
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
// GPIO /* ------- GPIO Group A ------- */
// NC PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_NC(GPD7, NONE), PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with pull up
PAD_NC(GPP_A7, NONE), // TPM_PIRQ#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with pull-up
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
PAD_NC(GPP_A11, NONE), // NC
PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_A18, NONE), // NC
PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // PS8338B_SW
PAD_NC(GPP_A23, NONE), // PS8338B_PCH
// Clock Signals /* ------- GPIO Group B ------- */
// SUS_CLK PAD_NC(GPP_B0, NONE), // CORE_VID0
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_NC(GPP_B1, NONE), // CORE_VID1
PAD_NC(GPP_B2, NONE), // CNVI_WAKE#
PAD_NC(GPP_B3, NONE), // NC
PAD_NC(GPP_B4, NONE), // NC
PAD_NC(GPP_B5, NONE), // NC
PAD_NC(GPP_B6, NONE), // NC
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
PAD_NC(GPP_B23, NONE), // NC
// Power Management /* ------- GPIO Group C ------- */
// GPD9_RTD3 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_NC(GPD9, NONE), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
// NC PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with pull-up
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), PAD_NC(GPP_C3, NONE), // NC
// NC PAD_NC(GPP_C4, NONE), // NC
PAD_NC(GPD11, NONE), PAD_NC(GPP_C5, NONE), // NC
PAD_NC(GPP_C6, NONE), // LAN_WAKEUP#
PAD_NC(GPP_C7, NONE), // NC
PAD_NC(GPP_C8, NONE), // NC
_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
PAD_NC(GPP_C11, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBTA_HRESET
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
PAD_NC(GPP_C18, NONE), // NC
PAD_NC(GPP_C19, NONE), // SWI
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE), // NC
PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
// GPP_A /* ------- GPIO Group D ------- */
// LPC PAD_NC(GPP_D0, NONE), // NC
// SB_KBCRST# PAD_NC(GPP_D1, NONE), // NC
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), PAD_NC(GPP_D2, NONE), // NC
// LPC_AD0 PAD_NC(GPP_D3, NONE), // NC
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), PAD_NC(GPP_D4, NONE), // NC
// LPC_AD1 PAD_NC(GPP_D5, NONE), // NC
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), PAD_NC(GPP_D6, NONE), // NC
// LPC_AD2 PAD_NC(GPP_D7, NONE), // NC
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // SB_BLON
// LPC_AD3 _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), PAD_NC(GPP_D10, NONE), // NC
// LPC_FRAME# _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
// SERIRQ with pull up PAD_NC(GPP_D13, NONE), // NC
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // RTD3_3G_PW R_EN
PAD_NC(GPP_D17, NONE), // NC
PAD_NC(GPP_D18, NONE), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
PAD_NC(GPP_D21, NONE), // TPM_DET#
PAD_NC(GPP_D22, NONE), // TPM_TCM_Detect
PAD_NC(GPP_D23, NONE), // NC
// GSPI0 /* ------- GPIO Group E ------- */
// TPM_PIRQ# PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with pull-up
PAD_NC(GPP_A7, NONE), PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
PAD_NC(GPP_E3, NONE), // NC
PAD_NC(GPP_E4, NONE), // NC
PAD_NC(GPP_E5, NONE), // NC
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
PAD_NC(GPP_E7, NONE), // NC
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
PAD_NC(GPP_E10, NONE), // GPP_E10
PAD_NC(GPP_E11, NONE), // GPP_E11
PAD_NC(GPP_E12, NONE), // USB_OC#78
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_NC(GPP_E22, NONE), // NC
PAD_NC(GPP_E23, NONE), // NC
// LPC /* ------- GPIO Group F ------- */
// PM_CLKRUN# with pull-up PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_NC(GPP_F1, NONE), // NC
// PCLK_KBC PAD_NC(GPP_F2, NONE), // NC
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), PAD_NC(GPP_F3, NONE), // NC
// NC PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_F10, NONE), // NC
PAD_NC(GPP_F11, NONE), // NC
PAD_NC(GPP_F12, NONE), // NC
PAD_NC(GPP_F13, NONE), // NC
PAD_NC(GPP_F14, NONE), // NC
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_NC(GPP_F19, NONE), // NC
PAD_NC(GPP_F20, NONE), // NC
PAD_NC(GPP_F21, NONE), // NC
PAD_NC(GPP_F22, NONE), // NC
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // A4WP_PRESENT
// GSPI1 /* ------- GPIO Group G ------- */
// NC PAD_NC(GPP_G0, NONE), // EDP_DET
PAD_NC(GPP_A11, NONE), PAD_NC(GPP_G1, NONE), // NC
PAD_NC(GPP_G2, NONE), // NC
PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
PAD_NC(GPP_G5, NONE), // BOARD_ID
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // TBT_Detect
// ISH_GP /* ------- GPIO Group H ------- */
// PCH_GPP_A12 PAD_NC(GPP_H0, NONE), // NC
PAD_NC(GPP_A12, NONE), PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
// Power Management PAD_NC(GPP_H3, NONE), // NC
// SUSWARN# PAD_NC(GPP_H4, NONE), // T23
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_NC(GPP_H5, NONE), // T22
PAD_NC(GPP_H6, NONE), // NC
// LPC PAD_NC(GPP_H7, NONE), // NC
// NC PAD_NC(GPP_H8, NONE), // NC
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), PAD_NC(GPP_H9, NONE), // NC
PAD_NC(GPP_H10, NONE), // NC
// Power Management PAD_NC(GPP_H11, NONE), // NC
// SUS_PWR_ACK PAD_NC(GPP_H12, NONE), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_NC(GPP_H13, NONE), // NC
PAD_NC(GPP_H14, NONE), // G_INT1
// SD PAD_NC(GPP_H15, NONE), // NC
// NC PAD_NC(GPP_H16, NONE), // NC
PAD_NC(GPP_A16, NONE), PAD_NC(GPP_H17, NONE), // NC
// LIGHT_KB_DET# PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_A17, NONE), PAD_NC(GPP_H19, NONE), // NC
PAD_NC(GPP_H20, NONE), // NC
// ISH_GP PAD_NC(GPP_H21, NONE), // GPPC_H21
// NC PAD_NC(GPP_H22, NONE), // TBT_RTD3_PWR_EN_R
PAD_NC(GPP_A18, NONE), PAD_NC(GPP_H23, NONE), // NC, WIGIG_PEWAKE
// SATA_PWR_EN
PAD_CFG_GPO(GPP_A19, 1, DEEP),
// NC
PAD_NC(GPP_A20, NONE),
// NC
PAD_NC(GPP_A21, NONE),
// PS8338B_SW
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
// PS8338B_PCH
PAD_NC(GPP_A23, NONE),
// GPP_B
// Power
// CORE_VID0
PAD_NC(GPP_B0, NONE),
// CORE_VID1
PAD_NC(GPP_B1, NONE),
// Power Management
// CNVI_WAKE#
PAD_NC(GPP_B2, NONE),
// CPU Misc
// NC
PAD_NC(GPP_B3, NONE),
// NC
PAD_NC(GPP_B4, NONE),
// Clock Signals
// NC
PAD_NC(GPP_B5, NONE),
// NC
PAD_NC(GPP_B6, NONE),
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
// LAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
// TBT_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
// Power Management
// EXT_PWR_GATE#
PAD_NC(GPP_B11, NONE),
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// SPKR
// PCH_SPKR
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
// GSPI0
// NC
PAD_NC(GPP_B15, NONE),
// PCH_GPP_B16
PAD_NC(GPP_B16, NONE),
// PCH_GPP_B17
PAD_NC(GPP_B17, NONE),
// PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B18, NONE),
// GSPI1
// NC
PAD_NC(GPP_B19, NONE),
// NC
PAD_NC(GPP_B20, NONE),
// NC
PAD_NC(GPP_B21, NONE),
// PCH_GPP_B22
PAD_NC(GPP_B22, NONE),
// SMBUS
// NC
PAD_NC(GPP_B23, NONE),
// GPP_C
// SMBUS
// SMB_CLK_DDR
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DAT_DDR
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// PCH_GPP_C2 with pull-up
PAD_NC(GPP_C2, NONE),
// NC
PAD_NC(GPP_C3, NONE),
// NC
PAD_NC(GPP_C4, NONE),
// NC
PAD_NC(GPP_C5, NONE),
// LAN_WAKEUP#
PAD_NC(GPP_C6, NONE),
// NC
PAD_NC(GPP_C7, NONE),
// UART0
// NC
PAD_NC(GPP_C8, NONE),
// TBCIO_PLUG_EVENT
_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
// TBT_FRC_PWR
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
// NC
PAD_NC(GPP_C11, NONE),
// UART1
// GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
// SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
// TBTA_HRESET
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
// TBT_PERST_N
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
// I2C
// T_SDA
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
// T_SCL
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C18, NONE),
// SWI
PAD_NC(GPP_C19, NONE),
// UART2
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// TP_ATTN#
PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
// GPP_D
// SPI1
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_D4, NONE),
// I2C
// NC
PAD_NC(GPP_D5, NONE),
// NC
PAD_NC(GPP_D6, NONE),
// NC
PAD_NC(GPP_D7, NONE),
// SB_BLON
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
// GSPI2
// SWI#
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
// NC
PAD_NC(GPP_D10, NONE),
// RTD3_PCIE_WAKE#
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
// PCH_GPP_D12
PAD_NC(GPP_D12, NONE),
// UART0
// NC
PAD_NC(GPP_D13, NONE),
// NC
PAD_NC(GPP_D14, NONE),
// NC
PAD_NC(GPP_D15, NONE),
// RTD3_3G_PW R_EN
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
// DMIC
// NC
PAD_NC(GPP_D17, NONE),
// NC
PAD_NC(GPP_D18, NONE),
// GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
// GPPC_DMIC_DATA
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
// SPI1
// TPM_DET#
PAD_NC(GPP_D21, NONE),
// TPM_TCM_Detect
PAD_NC(GPP_D22, NONE),
// I2S
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// PCH_GPP_E0 with pull-up
PAD_NC(GPP_E0, NONE),
// SATA_ODD_PRSNT#
PAD_NC(GPP_E1, NONE),
// SATAGP2
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E3, NONE),
// DEVSLP
// NC
PAD_NC(GPP_E4, NONE),
// NC
PAD_NC(GPP_E5, NONE),
// DEVSLP2
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E7, NONE),
// SATA
// PCH_SATAHDD_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB2
// GP_BSSB_CLK
PAD_NC(GPP_E9, NONE),
// GPP_E10
PAD_NC(GPP_E10, NONE),
// GPP_E11
PAD_NC(GPP_E11, NONE),
// USB_OC#78
PAD_NC(GPP_E12, NONE),
// Display Signals
// MUX_HPD
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
// HDMI_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
// SMI#
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
// SCI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
// EDP_HPD
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
// MDP_CTRLCLK
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
// MDP_CTRLDATA
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_E22, NONE),
// NC
PAD_NC(GPP_E23, NONE),
// GPP_F
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
// CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
// CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F10, NONE),
// EMMC
// NC
PAD_NC(GPP_F11, NONE),
// NC
PAD_NC(GPP_F12, NONE),
// NC
PAD_NC(GPP_F13, NONE),
// NC
PAD_NC(GPP_F14, NONE),
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// NC
PAD_NC(GPP_F19, NONE),
// NC
PAD_NC(GPP_F20, NONE),
// NC
PAD_NC(GPP_F21, NONE),
// NC
PAD_NC(GPP_F22, NONE),
// A4WP
// A4WP_PRESENT
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
// GPP_G
// SD
// EDP_DET
PAD_NC(GPP_G0, NONE),
// NC
PAD_NC(GPP_G1, NONE),
// NC
PAD_NC(GPP_G2, NONE),
// ASM1543_I_SEL0
PAD_NC(GPP_G3, NONE),
// ASM1543_I_SEL1
PAD_NC(GPP_G4, NONE),
// BOARD_ID
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// TBT_Detect
PAD_NC(GPP_G7, NONE),
// GPP_H
// CNVI
// NC
PAD_NC(GPP_H0, NONE),
// CNVI_RST#
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
// CNVI_CLKREQ
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
// NC
PAD_NC(GPP_H3, NONE),
// I2C
// T23
PAD_NC(GPP_H4, NONE),
// T22
PAD_NC(GPP_H5, NONE),
// NC
PAD_NC(GPP_H6, NONE),
// NC
PAD_NC(GPP_H7, NONE),
// NC
PAD_NC(GPP_H8, NONE),
// NC
PAD_NC(GPP_H9, NONE),
// I2C
// NC
PAD_NC(GPP_H10, NONE),
// NC
PAD_NC(GPP_H11, NONE),
// PCIE
// NC
PAD_NC(GPP_H12, NONE),
// NC
PAD_NC(GPP_H13, NONE),
// G_INT1
PAD_NC(GPP_H14, NONE),
// NC
PAD_NC(GPP_H15, NONE),
// Display Signals
// NC
PAD_NC(GPP_H16, NONE),
// NC
PAD_NC(GPP_H17, NONE),
// CPU Power
// CPU_C10_GATE#
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
// TIMESYNC
// NC
PAD_NC(GPP_H19, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_H20, NONE),
// GPIO
// GPPC_H21
PAD_NC(GPP_H21, NONE),
// TBT_RTD3_PWR_EN_R
PAD_NC(GPP_H22, NONE),
// NC, WIGIG_PEWAKE
PAD_NC(GPP_H23, NONE),
}; };
#endif #endif

View File

@ -10,596 +10,265 @@
/* Early pad configuration in romstage. */ /* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_NC(GPP_C22, NONE), // NC
// UART2_TXD PAD_NC(GPP_C23, NONE), // NC
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // NC
// NC PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
// AC_PRESENT PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
// NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD2, NATIVE, PWROK), _PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000), // NC
// PWR_BTN# _PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
// SUSB#_PCH PAD_CFG_GPI(GPD9, NONE, PWROK), // NC
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // NC
// SUSC#_PCH PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), // NC
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
// GPIO /* ------- GPIO Group A ------- */
// NC PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // TODO: LAN_WAKEUP#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // SUSWARN#
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE), // NC
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // NC
// Power Management /* ------- GPIO Group B ------- */
// SUS_CLK_R PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TODO: TPM_PIRQ#
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), // NC
// NC PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
PAD_CFG_GPI(GPD9, NONE, PWROK), PAD_CFG_GPI(GPP_B3, NONE, DEEP), // NC
// NC PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // TODO: EXTTS_SNI_DRV1
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), PAD_CFG_GPI(GPP_B5, NONE, PLTRST), // NC
// NC PAD_CFG_GPI(GPP_B6, NONE, PLTRST), // NC
PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), PAD_CFG_GPI(GPP_B7, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
// GPP_A /* ------- GPIO Group C ------- */
// LPC PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
// SB_KBCRST# PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_C2, NONE, DEEP), // NC
// LPC_AD0 PAD_NC(GPP_C3, NONE), // NC
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), PAD_NC(GPP_C4, NONE), // NC
// LPC_AD1 PAD_CFG_GPI(GPP_C5, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
// LPC_AD2 PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), PAD_NC(GPP_C8, NONE), // NC
// LPC_AD3 PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP), // TODO: CNVI_DET#
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), PAD_NC(GPP_C10, NONE), // NC
// LPC_FRAME# PAD_NC(GPP_C11, NONE), // NC
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_NC(GPP_C12, NONE), // NC
// SERIRQ PAD_NC(GPP_C13, NONE), // NC
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_NC(GPP_C14, NONE), // NC
// NC PAD_NC(GPP_C15, NONE), // NC
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SCL_TP
// PM_CLKRUN# PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_NC(GPP_C18, NONE), // NC
// PCLK_KBC PAD_NC(GPP_C19, NONE), // NC
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// NC PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // NC
// Power Management /* ------- GPIO Group D ------- */
// TODO: LAN_WAKEUP# PAD_NC(GPP_D0, NONE), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), PAD_NC(GPP_D1, NONE), // NC
// NC PAD_NC(GPP_D2, NONE), // NC
PAD_CFG_GPI(GPP_A12, NONE, DEEP), PAD_NC(GPP_D3, NONE), // NC
// SUSWARN# PAD_NC(GPP_D4, NONE), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE), // NC
PAD_NC(GPP_D8, NONE), // NC
PAD_NC(GPP_D9, NONE), // NC
PAD_NC(GPP_D10, NONE), // NC
PAD_NC(GPP_D11, NONE), // NC
PAD_NC(GPP_D12, NONE), // NC
PAD_NC(GPP_D13, NONE), // NC
PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_NC(GPP_D16, NONE), // NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
PAD_NC(GPP_D21, NONE), // NC
PAD_NC(GPP_D22, NONE), // NC
PAD_NC(GPP_D23, NONE), // NC
// LPC /* ------- GPIO Group E ------- */
// NC PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000), // TODO: EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // NC
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), // TODO: TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE), // NC
PAD_NC(GPP_E10, NONE), // NC
PAD_NC(GPP_E11, NONE), // NC
PAD_NC(GPP_E12, NONE), // NC
// Power Management /* ------- GPIO Group F ------- */
// SUS_PWR_ACK PAD_NC(GPP_F0, NONE), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), PAD_NC(GPP_F1, NONE), // NC
PAD_NC(GPP_F2, NONE), // NC
PAD_NC(GPP_F3, NONE), // NC
PAD_NC(GPP_F4, NONE), // NC
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE), // NC
PAD_NC(GPP_F8, NONE), // NC
PAD_NC(GPP_F9, NONE), // NC
PAD_NC(GPP_F10, NONE), // BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F13, NONE), // TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST), // TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // TODO: DGPU_PWR_EN
// Clock Signals /* ------- GPIO Group G ------- */
// NC PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_NC(GPP_A16, NONE), PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE), // NC
PAD_NC(GPP_G5, NONE), // NC
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // NC
// ISH /* ------- GPIO Group H ------- */
// NC PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_NC(GPP_A17, NONE), _PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000), // NC
// SB_BLON PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), _PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000), // NC
// NC PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_NC(GPP_A19, NONE), PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
// NC _PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000), // NC
PAD_NC(GPP_A20, NONE), _PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000), // NC
// NC _PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000), // NC
PAD_NC(GPP_A21, NONE), _PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000), // NC
// SATA_PWR_EN PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
// NC PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 - strap for ESPI flash sharing mode
PAD_NC(GPP_A23, NONE), PAD_CFG_GPI(GPP_H13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // NC
// GPP_B /* ------- GPIO Group I ------- */
// GSPI PAD_CFG_GPI(GPP_I0, NONE, DEEP), // NC
// TODO: TPM_PIRQ# PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_B0, NONE, DEEP), PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // NC
// NC _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_GPI(GPP_I5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
// Power Management /* ------- GPIO Group J ------- */
// NC PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_B2, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // NC
PAD_NC(GPP_J2, NONE), // NC
PAD_NC(GPP_J3, NONE), // NC
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE), // NC
PAD_NC(GPP_J11, NONE), // NC
// CPU Misc /* ------- GPIO Group K ------- */
// NC PAD_NC(GPP_K0, NONE), // NC
PAD_CFG_GPI(GPP_B3, NONE, DEEP), PAD_NC(GPP_K1, NONE), // NC
// TODO: EXTTS_SNI_DRV1 PAD_NC(GPP_K2, NONE), // NC
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, NONE), // NC
// Clock Signals PAD_NC(GPP_K5, NONE), // NC
// NC _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), // SWI#
PAD_CFG_GPI(GPP_B5, NONE, PLTRST), PAD_NC(GPP_K7, NONE), // NC
// NC PAD_CFG_GPI(GPP_K8, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_B6, NONE, PLTRST), PAD_CFG_GPI(GPP_K9, NONE, DEEP), // SATA_M2_PWR_EN2
// NC PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B7, NONE, PLTRST), PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
// NC PAD_NC(GPP_K12, NONE), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), PAD_NC(GPP_K13, NONE), // NC
// NC PAD_NC(GPP_K14, NONE), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), PAD_NC(GPP_K15, NONE), // NC
// LAN_CLKREQ# PAD_NC(GPP_K16, NONE), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), PAD_NC(GPP_K17, NONE), // NC
PAD_NC(GPP_K18, NONE), // NC
// Audio _PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), // SMI#
// TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V _PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000), // TODO: GPU_EVENT#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), PAD_CFG_GPI(GPP_K21, NONE, DEEP), // TODO: GC6_FB_EN_PCH
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000), // TODO: DGPU_PWRGD_R
// Power Management PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1), // NC
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// Audio
// PCH_SPKR
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
// GSPI
// NC
PAD_NC(GPP_B15, NONE),
// NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
// LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_B19, NONE),
// NC
PAD_NC(GPP_B20, NONE),
// NC
PAD_NC(GPP_B21, NONE),
// LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
// SMBUS
// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
// GPP_C
// SMBUS
// SMB_CLK
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DATA
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
// NC
PAD_NC(GPP_C3, NONE),
// NC
PAD_NC(GPP_C4, NONE),
// NC
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
// UART
// NC
PAD_NC(GPP_C8, NONE),
// TODO: CNVI_DET#
PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
// NC
PAD_NC(GPP_C10, NONE),
// NC
PAD_NC(GPP_C11, NONE),
// NC
PAD_NC(GPP_C12, NONE),
// NC
PAD_NC(GPP_C13, NONE),
// NC
PAD_NC(GPP_C14, NONE),
// NC
PAD_NC(GPP_C15, NONE),
// I2C
// I2C_SCL_TP
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
// I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
// NC
PAD_NC(GPP_C18, NONE),
// NC
PAD_NC(GPP_C19, NONE),
// UART
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
// GPP_D
// SPI
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// I2C
// NC
PAD_NC(GPP_D4, NONE),
// CNVI
// CNVI_RF_RST#
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
// XTAL_CLKREQ
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
// NC
PAD_NC(GPP_D7, NONE),
// NC
PAD_NC(GPP_D8, NONE),
// ISH
// NC
PAD_NC(GPP_D9, NONE),
// NC
PAD_NC(GPP_D10, NONE),
// NC
PAD_NC(GPP_D11, NONE),
// NC
PAD_NC(GPP_D12, NONE),
// NC
PAD_NC(GPP_D13, NONE),
// NC
PAD_NC(GPP_D14, NONE),
// NC
PAD_NC(GPP_D15, NONE),
// NC
PAD_NC(GPP_D16, NONE),
// DMIC
// NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
// SPI
// NC
PAD_NC(GPP_D21, NONE),
// NC
PAD_NC(GPP_D22, NONE),
// ISH
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// NC
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
// SATAGP1
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
// CPU Misc
// TODO: EXTTS_SNI_DRV0
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
// SATA
// DEVSLP0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
// DEVSLP1
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
// NC
PAD_NC(GPP_E6, NONE),
// CPU Misc
// TODO: TP_ATTN#
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
// SATA
// SATA_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB2
// NC
PAD_NC(GPP_E9, NONE),
// NC
PAD_NC(GPP_E10, NONE),
// NC
PAD_NC(GPP_E11, NONE),
// NC
PAD_NC(GPP_E12, NONE),
// GPP_F
// SATA
// NC
PAD_NC(GPP_F0, NONE),
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// NC
PAD_NC(GPP_F4, NONE),
// KBLED_DET
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
// LIGHT_KB_DET#
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
// NC
PAD_NC(GPP_F7, NONE),
// NC
PAD_NC(GPP_F8, NONE),
// NC
PAD_NC(GPP_F9, NONE),
// BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F10, NONE),
// PCH_RSVD - unused strap
PAD_NC(GPP_F11, NONE),
// MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F12, NONE),
// TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_NC(GPP_F13, NONE),
// Power Management
// H_SKTOCC_N
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
// USB2
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// Display Signals
// NB_ENAVDD
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
// BLON
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
// EDP_BRIGHTNESS
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
// TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
// TODO: DGPU_PWR_EN
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
// GPP_G
// SD
// BOARD_ID1
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
// BOARD_ID2
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
// TPM_DET
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
// TODO: GPIO4_1V8_MAIN_EN_R
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
// NC
PAD_NC(GPP_G4, NONE),
// NC
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// NC
PAD_NC(GPP_G7, NONE),
// GPP_H
// Clock Signals
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
// PEG_CLKREQ#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
// SSD2_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
// SMBUS
// NC
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
// GPP_H_12 - strap for ESPI flash sharing mode
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
// ISH
// NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
// GPIO
// NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
// GPP_I
// Display Signals
// NC
PAD_CFG_GPI(GPP_I0, NONE, DEEP),
// HDMI_HPD
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
// NC
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
// MDP_E_HPD
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
// EDP_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_I5, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_I9, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
// PCIE
// TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I12, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
// GPP_J
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
// Power Management
// NC
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
// GPIO
// NC
PAD_NC(GPP_J2, NONE),
// NC
PAD_NC(GPP_J3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
// CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
// CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_J10, NONE),
// A4WP
// NC
PAD_NC(GPP_J11, NONE),
// GPP_K
// GPIO
// NC
PAD_NC(GPP_K0, NONE),
// NC
PAD_NC(GPP_K1, NONE),
// NC
PAD_NC(GPP_K2, NONE),
// SCI#
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
// NC
PAD_NC(GPP_K4, NONE),
// NC
PAD_NC(GPP_K5, NONE),
// SWI#
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
// NC
PAD_NC(GPP_K7, NONE),
// SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_K8, NONE, DEEP),
// SATA_M2_PWR_EN2
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
// GSX
// NC
PAD_NC(GPP_K12, NONE),
// NC
PAD_NC(GPP_K13, NONE),
// NC
PAD_NC(GPP_K14, NONE),
// NC
PAD_NC(GPP_K15, NONE),
// NC
PAD_NC(GPP_K16, NONE),
// GPIO
// NC
PAD_NC(GPP_K17, NONE),
// NC
PAD_NC(GPP_K18, NONE),
// SMI#
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
// TODO: GPU_EVENT#
_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
// TODO: GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
// TODO: DGPU_PWRGD_R
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
// NC
PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
}; };
#endif #endif

View File

@ -10,596 +10,265 @@
/* Early pad configuration in romstage. */ /* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_NC(GPP_C22, NONE), // NC
// UART2_TXD PAD_NC(GPP_C23, NONE), // NC
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // NC
// NC PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
// AC_PRESENT PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
// NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_GPI(GPD2, NATIVE, PWROK), _PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000), // NC
// PWR_BTN# _PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
// SUSB#_PCH PAD_CFG_GPI(GPD9, NONE, PWROK), // NC
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // NC
// SUSC#_PCH PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), // NC
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
// GPIO /* ------- GPIO Group A ------- */
// NC PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // TODO: LAN_WAKEUP#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // SUSWARN#
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE), // NC
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // NC
// Power Management /* ------- GPIO Group B ------- */
// SUS_CLK_R PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TODO: TPM_PIRQ#
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), // NC
// NC PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
PAD_CFG_GPI(GPD9, NONE, PWROK), PAD_CFG_GPI(GPP_B3, NONE, DEEP), // NC
// NC PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // TODO: EXTTS_SNI_DRV1
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), PAD_CFG_GPI(GPP_B5, NONE, PLTRST), // NC
// NC PAD_CFG_GPI(GPP_B6, NONE, PLTRST), // NC
PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), PAD_CFG_GPI(GPP_B7, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
// GPP_A /* ------- GPIO Group C ------- */
// LPC PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
// SB_KBCRST# PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_C2, NONE, DEEP), // NC
// LPC_AD0 PAD_NC(GPP_C3, NONE), // NC
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), PAD_NC(GPP_C4, NONE), // NC
// LPC_AD1 PAD_CFG_GPI(GPP_C5, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
// LPC_AD2 PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), PAD_NC(GPP_C8, NONE), // NC
// LPC_AD3 PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP), // TODO: CNVI_DET#
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), PAD_NC(GPP_C10, NONE), // NC
// LPC_FRAME# PAD_NC(GPP_C11, NONE), // NC
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_NC(GPP_C12, NONE), // NC
// SERIRQ PAD_NC(GPP_C13, NONE), // NC
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_NC(GPP_C14, NONE), // NC
// NC PAD_NC(GPP_C15, NONE), // NC
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SCL_TP
// PM_CLKRUN# PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_NC(GPP_C18, NONE), // NC
// PCLK_KBC PAD_NC(GPP_C19, NONE), // NC
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// NC PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // NC
// Power Management /* ------- GPIO Group D ------- */
// TODO: LAN_WAKEUP# PAD_NC(GPP_D0, NONE), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), PAD_NC(GPP_D1, NONE), // NC
// NC PAD_NC(GPP_D2, NONE), // NC
PAD_CFG_GPI(GPP_A12, NONE, DEEP), PAD_NC(GPP_D3, NONE), // NC
// SUSWARN# PAD_NC(GPP_D4, NONE), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE), // NC
PAD_NC(GPP_D8, NONE), // NC
PAD_NC(GPP_D9, NONE), // NC
PAD_NC(GPP_D10, NONE), // NC
PAD_NC(GPP_D11, NONE), // NC
PAD_NC(GPP_D12, NONE), // NC
PAD_NC(GPP_D13, NONE), // NC
PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_NC(GPP_D16, NONE), // NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
PAD_NC(GPP_D21, NONE), // NC
PAD_NC(GPP_D22, NONE), // NC
PAD_NC(GPP_D23, NONE), // NC
// LPC /* ------- GPIO Group E ------- */
// NC PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000), // TODO: EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // NC
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), // TODO: TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE), // NC
PAD_NC(GPP_E10, NONE), // NC
PAD_NC(GPP_E11, NONE), // NC
PAD_NC(GPP_E12, NONE), // NC
// Power Management /* ------- GPIO Group F ------- */
// SUS_PWR_ACK PAD_NC(GPP_F0, NONE), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), PAD_NC(GPP_F1, NONE), // NC
PAD_NC(GPP_F2, NONE), // NC
PAD_NC(GPP_F3, NONE), // NC
PAD_NC(GPP_F4, NONE), // NC
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE), // NC
PAD_NC(GPP_F8, NONE), // NC
PAD_NC(GPP_F9, NONE), // NC
PAD_NC(GPP_F10, NONE), // BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F13, NONE), // TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST), // TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // TODO: DGPU_PWR_EN
// Clock Signals /* ------- GPIO Group G ------- */
// NC PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_NC(GPP_A16, NONE), PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE), // NC
PAD_NC(GPP_G5, NONE), // NC
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // NC
// ISH /* ------- GPIO Group H ------- */
// NC PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_NC(GPP_A17, NONE), _PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000), // NC
// SB_BLON PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), _PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000), // NC
// NC PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_NC(GPP_A19, NONE), PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
// NC _PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000), // NC
PAD_NC(GPP_A20, NONE), _PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000), // NC
// NC _PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000), // NC
PAD_NC(GPP_A21, NONE), _PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000), // NC
// SATA_PWR_EN PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
// NC PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 - strap for ESPI flash sharing mode
PAD_NC(GPP_A23, NONE), PAD_CFG_GPI(GPP_H13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // NC
// GPP_B /* ------- GPIO Group I ------- */
// GSPI PAD_CFG_GPI(GPP_I0, NONE, DEEP), // NC
// TODO: TPM_PIRQ# PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_B0, NONE, DEEP), PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // NC
// NC _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_GPI(GPP_I5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
// Power Management /* ------- GPIO Group J ------- */
// NC PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPI(GPP_B2, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // NC
PAD_NC(GPP_J2, NONE), // NC
PAD_NC(GPP_J3, NONE), // NC
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE), // NC
PAD_NC(GPP_J11, NONE), // NC
// CPU Misc /* ------- GPIO Group K ------- */
// NC PAD_NC(GPP_K0, NONE), // NC
PAD_CFG_GPI(GPP_B3, NONE, DEEP), PAD_NC(GPP_K1, NONE), // NC
// TODO: EXTTS_SNI_DRV1 PAD_NC(GPP_K2, NONE), // NC
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, NONE), // NC
// Clock Signals PAD_NC(GPP_K5, NONE), // NC
// NC _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), // SWI#
PAD_CFG_GPI(GPP_B5, NONE, PLTRST), PAD_NC(GPP_K7, NONE), // NC
// NC PAD_CFG_GPI(GPP_K8, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_B6, NONE, PLTRST), PAD_CFG_GPI(GPP_K9, NONE, DEEP), // SATA_M2_PWR_EN2
// NC PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B7, NONE, PLTRST), PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
// NC PAD_NC(GPP_K12, NONE), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), PAD_NC(GPP_K13, NONE), // NC
// NC PAD_NC(GPP_K14, NONE), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), PAD_NC(GPP_K15, NONE), // NC
// LAN_CLKREQ# PAD_NC(GPP_K16, NONE), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), PAD_NC(GPP_K17, NONE), // NC
PAD_NC(GPP_K18, NONE), // NC
// Audio _PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), // SMI#
// TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V _PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000), // TODO: GPU_EVENT#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), PAD_CFG_GPI(GPP_K21, NONE, DEEP), // TODO: GC6_FB_EN_PCH
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000), // TODO: DGPU_PWRGD_R
// Power Management PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1), // NC
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// Audio
// PCH_SPKR
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
// GSPI
// NC
PAD_NC(GPP_B15, NONE),
// NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
// LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_B19, NONE),
// NC
PAD_NC(GPP_B20, NONE),
// NC
PAD_NC(GPP_B21, NONE),
// LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
// SMBUS
// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
// GPP_C
// SMBUS
// SMB_CLK
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DATA
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
// NC
PAD_NC(GPP_C3, NONE),
// NC
PAD_NC(GPP_C4, NONE),
// NC
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
// UART
// NC
PAD_NC(GPP_C8, NONE),
// TODO: CNVI_DET#
PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
// NC
PAD_NC(GPP_C10, NONE),
// NC
PAD_NC(GPP_C11, NONE),
// NC
PAD_NC(GPP_C12, NONE),
// NC
PAD_NC(GPP_C13, NONE),
// NC
PAD_NC(GPP_C14, NONE),
// NC
PAD_NC(GPP_C15, NONE),
// I2C
// I2C_SCL_TP
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
// I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
// NC
PAD_NC(GPP_C18, NONE),
// NC
PAD_NC(GPP_C19, NONE),
// UART
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
// GPP_D
// SPI
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// I2C
// NC
PAD_NC(GPP_D4, NONE),
// CNVI
// CNVI_RF_RST#
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
// XTAL_CLKREQ
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
// NC
PAD_NC(GPP_D7, NONE),
// NC
PAD_NC(GPP_D8, NONE),
// ISH
// NC
PAD_NC(GPP_D9, NONE),
// NC
PAD_NC(GPP_D10, NONE),
// NC
PAD_NC(GPP_D11, NONE),
// NC
PAD_NC(GPP_D12, NONE),
// NC
PAD_NC(GPP_D13, NONE),
// NC
PAD_NC(GPP_D14, NONE),
// NC
PAD_NC(GPP_D15, NONE),
// NC
PAD_NC(GPP_D16, NONE),
// DMIC
// NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
// NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
// SPI
// NC
PAD_NC(GPP_D21, NONE),
// NC
PAD_NC(GPP_D22, NONE),
// ISH
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// NC
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
// SATAGP1
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
// CPU Misc
// TODO: EXTTS_SNI_DRV0
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
// SATA
// DEVSLP0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
// DEVSLP1
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
// NC
PAD_NC(GPP_E6, NONE),
// CPU Misc
// TODO: TP_ATTN#
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
// SATA
// SATA_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB2
// NC
PAD_NC(GPP_E9, NONE),
// NC
PAD_NC(GPP_E10, NONE),
// NC
PAD_NC(GPP_E11, NONE),
// NC
PAD_NC(GPP_E12, NONE),
// GPP_F
// SATA
// NC
PAD_NC(GPP_F0, NONE),
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// NC
PAD_NC(GPP_F4, NONE),
// KBLED_DET
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
// LIGHT_KB_DET#
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
// NC
PAD_NC(GPP_F7, NONE),
// NC
PAD_NC(GPP_F8, NONE),
// NC
PAD_NC(GPP_F9, NONE),
// BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F10, NONE),
// PCH_RSVD - unused strap
PAD_NC(GPP_F11, NONE),
// MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F12, NONE),
// TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_NC(GPP_F13, NONE),
// Power Management
// H_SKTOCC_N
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
// USB2
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// Display Signals
// NB_ENAVDD
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
// BLON
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
// EDP_BRIGHTNESS
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
// TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
// TODO: DGPU_PWR_EN
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
// GPP_G
// SD
// BOARD_ID1
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
// BOARD_ID2
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
// TPM_DET
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
// TODO: GPIO4_1V8_MAIN_EN_R
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
// NC
PAD_NC(GPP_G4, NONE),
// NC
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// NC
PAD_NC(GPP_G7, NONE),
// GPP_H
// Clock Signals
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
// PEG_CLKREQ#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
// SSD2_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
// NC
_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
// NC
_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
// SMBUS
// NC
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
// GPP_H_12 - strap for ESPI flash sharing mode
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
// ISH
// NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
// GPIO
// NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
// GPP_I
// Display Signals
// NC
PAD_CFG_GPI(GPP_I0, NONE, DEEP),
// HDMI_HPD
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
// NC
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
// MDP_E_HPD
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
// EDP_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_I5, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
// NC
PAD_CFG_GPI(GPP_I9, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
// PCIE
// TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I12, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
// GPP_J
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
// Power Management
// NC
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
// GPIO
// NC
PAD_NC(GPP_J2, NONE),
// NC
PAD_NC(GPP_J3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
// CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
// CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_J10, NONE),
// A4WP
// NC
PAD_NC(GPP_J11, NONE),
// GPP_K
// GPIO
// NC
PAD_NC(GPP_K0, NONE),
// NC
PAD_NC(GPP_K1, NONE),
// NC
PAD_NC(GPP_K2, NONE),
// SCI#
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
// NC
PAD_NC(GPP_K4, NONE),
// NC
PAD_NC(GPP_K5, NONE),
// SWI#
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
// NC
PAD_NC(GPP_K7, NONE),
// SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_K8, NONE, DEEP),
// SATA_M2_PWR_EN2
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
// NC
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
// GSX
// NC
PAD_NC(GPP_K12, NONE),
// NC
PAD_NC(GPP_K13, NONE),
// NC
PAD_NC(GPP_K14, NONE),
// NC
PAD_NC(GPP_K15, NONE),
// NC
PAD_NC(GPP_K16, NONE),
// GPIO
// NC
PAD_NC(GPP_K17, NONE),
// NC
PAD_NC(GPP_K18, NONE),
// SMI#
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
// TODO: GPU_EVENT#
_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
// TODO: GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
// TODO: DGPU_PWRGD_R
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
// NC
PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
}; };
#endif #endif

View File

@ -8,433 +8,193 @@
#ifndef __ACPI__ #ifndef __ACPI__
// Pad configuration in ramstage
static const struct pad_config gpio_table[] = {
// GPD
// System Power Management
// PM_BATLOW#
PAD_NC(GPD0, NONE),
// AC_PRESENT
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
// LAN_WAKEUP#
_PAD_CFG_STRUCT(GPD2, 0x880500, 0x0),
// PWR_BTN#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
// SUSB#_PCH
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
// SUSC#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// SLP_A#
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
// NC
PAD_NC(GPD7, NONE),
// SUSCLK
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
// PCH_SLP_WLAN#
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
// SLP_S5#
PAD_NC(GPD10, NONE),
// PCH_GPD11
PAD_NC(GPD11, NONE),
// GPP_A
// LPC
// TODO - SB_KBCRST#
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
// LPC_AD0
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
// LPC_AD1
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
// LPC_AD2
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
// LPC_AD3
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
// LPC_FRAME#
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
// SERIRQ
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
// PCIE/USB3/SATA
// G_INT1
PAD_NC(GPP_A7, NONE),
// LPC
// PM_CLKRUN#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
// PCLK_KBC
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
// PCLK_TPM
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
// System Power Management
// TODO - LAN_WAKEUP#
PAD_NC(GPP_A11, NONE),
// ISH
// PCH_GPP_A12
PAD_NC(GPP_A12, NONE),
// System Power Management
// SUSWARN#
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
// LPC
// S4_STATE#
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
// System Power Management
// SUSACK#
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
// SDIO/SDXC
// NC
PAD_NC(GPP_A16, NONE),
// NC
PAD_NC(GPP_A17, NONE),
// ISH
// TBTA_ACE_GPIO3
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
// SATA_PWR_EN
PAD_CFG_GPO(GPP_A19, 1, DEEP),
// TBTA_ACE_GPIO0
PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP),
// TBT_FRC_PWR
PAD_CFG_TERM_GPO(GPP_A21, 1, DN_20K, PLTRST),
// PS8338B_SW
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, PWROK),
// PS8338B_PCH
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PWROK),
// GPP_B
// CPU Power
// CORE_VID0
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
// CORE_VID1
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
// System Power Management
// VRALERT#
PAD_NC(GPP_B2, NONE),
// CPU Misc
// NC
PAD_NC(GPP_B3, NONE),
// NC
PAD_NC(GPP_B4, NONE),
// Clock Signals
// PCIECLKRQ0#
PAD_NC(GPP_B5, NONE),
// PCIECLKRQ1#
PAD_NC(GPP_B6, NONE),
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
// LAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
// TBT_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
// System Power Management
// NC
PAD_NC(GPP_B11, NONE),
// SLP_S0#
PAD_NC(GPP_B12, NONE),
// PLTRST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// Audio - SPKR
// PCH_SPKR
PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1),
// LPSS
// PCH_GPP_B15
PAD_NC(GPP_B15, NONE),
// PCH_GPP_B16
PAD_NC(GPP_B16, NONE),
// PCH_GPP_B17
PAD_NC(GPP_B17, NONE),
// GSPI0_BBS0 - No Reboot strap
PAD_NC(GPP_B18, NONE),
// PCH_GPP_B19
PAD_NC(GPP_B19, NONE),
// PCH_GPP_B20
PAD_NC(GPP_B20, NONE),
// PCH_GPP_B21
PAD_NC(GPP_B21, NONE),
// PCH_GPP_B22 - Boot BIOS strap
PAD_NC(GPP_B22, NONE),
// SMBUS
// PCH_GPP_B23
PAD_NC(GPP_B23, NONE),
// GPP_C
// SMBUS
// SMB_CLK
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DATA
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// PCH_GPP_C2
PAD_NC(GPP_C2, NONE),
// SML0CLK
PAD_NC(GPP_C3, NONE),
// SML0DATA
PAD_NC(GPP_C4, NONE),
// PCH_GPP_C5
PAD_NC(GPP_C5, NONE),
// SML1CLK
PAD_NC(GPP_C6, NONE),
// SML1DATA
PAD_NC(GPP_C7, NONE),
// LPSS
// NC
PAD_NC(GPP_C8, NONE),
// NC
PAD_NC(GPP_C9, NONE),
// NC
PAD_NC(GPP_C10, NONE),
// NC
PAD_NC(GPP_C11, NONE),
// ISH
// TBTA_ACE_GPIO2
PAD_NC(GPP_C12, NONE),
// TBCIO_PLUG_EVENT
_PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000),
// TBTA_MRESET
PAD_NC(GPP_C14, NONE),
// TBTA_ACE_GPIO7
PAD_NC(GPP_C15, NONE),
// LPSS
// T_SDA
PAD_NC(GPP_C16, NONE),
// T_SCL
PAD_NC(GPP_C17, NONE),
// NC
PAD_NC(GPP_C18, NONE),
// SWI#
_PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000),
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// UEART2_RTS_N
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
// UART2_CTS_N
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
// GPP_D
// SPI - Touch
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// NC
PAD_NC(GPP_D4, NONE),
// ISH
// NC
PAD_NC(GPP_D5, NONE),
// NC
PAD_NC(GPP_D6, NONE),
// NC
PAD_NC(GPP_D7, NONE),
// SB_BLON
PAD_CFG_GPO(GPP_D8, 1, DEEP),
// T_INT
PAD_NC(GPP_D9, NONE),
// EDP_DET
PAD_NC(GPP_D10, NONE),
// NC
PAD_NC(GPP_D11, NONE),
// NC
PAD_NC(GPP_D12, NONE),
// NC
PAD_NC(GPP_D13, NONE),
// NC
PAD_NC(GPP_D14, NONE),
// NC
PAD_NC(GPP_D15, NONE),
// NC
PAD_NC(GPP_D16, NONE),
// Audio - DMIC
// NC
PAD_NC(GPP_D17, NONE),
// NC
PAD_NC(GPP_D18, NONE),
// NC
PAD_NC(GPP_D19, NONE),
// NC
PAD_NC(GPP_D20, NONE),
// SPI - Touch
// TPM_DET#
PAD_NC(GPP_D21, NONE),
// NC
PAD_NC(GPP_D22, NONE),
// Audio - I2S
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATAXPCIE
// PCH_GPP_E0
PAD_NC(GPP_E0, NONE),
// SATA_ODD_PRSNT#
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
// SATAGP2
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E3, NONE),
// DEVSLP
// DEVSLP0
PAD_NC(GPP_E4, NONE),
// DEVSLP1
PAD_NC(GPP_E5, NONE),
// DEVSLP2
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E7, NONE),
// USB2
// PCH_SATA_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB_OC#12
PAD_NC(GPP_E9, NONE),
// USB_OC#34
PAD_NC(GPP_E10, NONE),
// USB_OC#56
PAD_NC(GPP_E11, NONE),
// USB_OC#78
PAD_NC(GPP_E12, NONE),
// Display Sidebands
// MUX_HPD
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
// HDMI_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
// SMI#
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
// SCI#
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL),
// EDP_HPD
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
// MDP_CTRLCLK
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
// MDP_CTRLDATA
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
// NC
PAD_NC(GPP_E22, NONE),
// NC
PAD_NC(GPP_E23, NONE),
// GPP_F
// Audio - I2S
// NC
PAD_NC(GPP_F0, NONE),
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// LPSS
// NC
PAD_NC(GPP_F4, NONE),
// NC
PAD_NC(GPP_F5, NONE),
// NC
PAD_NC(GPP_F6, NONE),
// NC
PAD_NC(GPP_F7, NONE),
// NC
PAD_NC(GPP_F8, NONE),
// NC
PAD_NC(GPP_F9, NONE),
// ISH
// NC
PAD_NC(GPP_F10, NONE),
// NC
PAD_NC(GPP_F11, NONE),
// EMMC
// NC
PAD_NC(GPP_F12, NONE),
// NC
PAD_NC(GPP_F13, NONE),
// NC
PAD_NC(GPP_F14, NONE),
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// NC
PAD_NC(GPP_F19, NONE),
// NC
PAD_NC(GPP_F20, NONE),
// NC
PAD_NC(GPP_F21, NONE),
// NC
PAD_NC(GPP_F22, NONE),
// SDIO/SDXC
// LIGHT_KB_DET#
PAD_NC(GPP_F23, NONE),
// GPP_G
// SDIO/SDXC
// NC
PAD_NC(GPP_G0, NONE),
// TBT Detect
PAD_NC(GPP_G1, NONE),
// NC
PAD_NC(GPP_G2, NONE),
// ASM1543_I_SEL0
PAD_NC(GPP_G3, NONE),
// ASM1543_I_SEL1
PAD_NC(GPP_G4, NONE),
// NC
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// NC
PAD_NC(GPP_G7, NONE),
};
// Early pad configuration in romstage // Early pad configuration in romstage
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// LPSS PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), };
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // Pad configuration in ramstage
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_NC(GPD0, NONE), // PM_BATLOW#
PAD_CFG_NF(GPD1, NONE, DEEP, NF1), // AC_PRESENT
_PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
PAD_NC(GPD7, NONE), // NC
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK
PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // PCH_SLP_WLAN#
PAD_NC(GPD10, NONE), // SLP_S5#
PAD_NC(GPD11, NONE), // PCH_GPD11
/* ------- GPIO Group A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // TODO - SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_NC(GPP_A7, NONE), // G_INT1
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // PCLK_TPM
PAD_NC(GPP_A11, NONE), // TODO - LAN_WAKEUP#
PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE#
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUSACK#
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // TBTA_ACE_GPIO3
PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP), // TBTA_ACE_GPIO0
PAD_CFG_TERM_GPO(GPP_A21, 1, DN_20K, PLTRST), // TBT_FRC_PWR
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, PWROK), // PS8338B_SW
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PWROK), // PS8338B_PCH
/* ------- GPIO Group B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1
PAD_NC(GPP_B2, NONE), // VRALERT#
PAD_NC(GPP_B3, NONE), // NC
PAD_NC(GPP_B4, NONE), // NC
PAD_NC(GPP_B5, NONE), // PCIECLKRQ0#
PAD_NC(GPP_B6, NONE), // PCIECLKRQ1#
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_NC(GPP_B11, NONE), // NC
PAD_NC(GPP_B12, NONE), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // PCH_GPP_B15
PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
PAD_NC(GPP_B18, NONE), // GSPI0_BBS0 - No Reboot strap
PAD_NC(GPP_B19, NONE), // PCH_GPP_B19
PAD_NC(GPP_B20, NONE), // PCH_GPP_B20
PAD_NC(GPP_B21, NONE), // PCH_GPP_B21
PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - Boot BIOS strap
PAD_NC(GPP_B23, NONE), // PCH_GPP_B23
/* ------- GPIO Group C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_NC(GPP_C2, NONE), // PCH_GPP_C2
PAD_NC(GPP_C3, NONE), // SML0CLK
PAD_NC(GPP_C4, NONE), // SML0DATA
PAD_NC(GPP_C5, NONE), // PCH_GPP_C5
PAD_NC(GPP_C6, NONE), // SML1CLK
PAD_NC(GPP_C7, NONE), // SML1DATA
PAD_NC(GPP_C8, NONE), // NC
PAD_NC(GPP_C9, NONE), // NC
PAD_NC(GPP_C10, NONE), // NC
PAD_NC(GPP_C11, NONE), // NC
PAD_NC(GPP_C12, NONE), // TBTA_ACE_GPIO2
_PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT
PAD_NC(GPP_C14, NONE), // TBTA_MRESET
PAD_NC(GPP_C15, NONE), // TBTA_ACE_GPIO7
PAD_NC(GPP_C16, NONE), // T_SDA
PAD_NC(GPP_C17, NONE), // T_SCL
PAD_NC(GPP_C18, NONE), // NC
_PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000), // SWI#
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UEART2_RTS_N
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS_N
/* ------- GPIO Group D ------- */
PAD_NC(GPP_D0, NONE), // NC
PAD_NC(GPP_D1, NONE), // NC
PAD_NC(GPP_D2, NONE), // NC
PAD_NC(GPP_D3, NONE), // NC
PAD_NC(GPP_D4, NONE), // NC
PAD_NC(GPP_D5, NONE), // NC
PAD_NC(GPP_D6, NONE), // NC
PAD_NC(GPP_D7, NONE), // NC
PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
PAD_NC(GPP_D9, NONE), // T_INT
PAD_NC(GPP_D10, NONE), // EDP_DET
PAD_NC(GPP_D11, NONE), // NC
PAD_NC(GPP_D12, NONE), // NC
PAD_NC(GPP_D13, NONE), // NC
PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_NC(GPP_D16, NONE), // NC
PAD_NC(GPP_D17, NONE), // NC
PAD_NC(GPP_D18, NONE), // NC
PAD_NC(GPP_D19, NONE), // NC
PAD_NC(GPP_D20, NONE), // NC
PAD_NC(GPP_D21, NONE), // TPM_DET#
PAD_NC(GPP_D22, NONE), // NC
PAD_NC(GPP_D23, NONE), // NC
/* ------- GPIO Group E ------- */
PAD_NC(GPP_E0, NONE), // PCH_GPP_E0
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATA_ODD_PRSNT#
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), // SATAGP2
PAD_NC(GPP_E3, NONE), // NC
PAD_NC(GPP_E4, NONE), // DEVSLP0
PAD_NC(GPP_E5, NONE), // DEVSLP1
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
PAD_NC(GPP_E7, NONE), // NC
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATA_LED#
PAD_NC(GPP_E9, NONE), // USB_OC#12
PAD_NC(GPP_E10, NONE), // USB_OC#34
PAD_NC(GPP_E11, NONE), // USB_OC#56
PAD_NC(GPP_E12, NONE), // USB_OC#78
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI#
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), // MDP_CTRLDATA
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), // HDMI_CTRLDATA
PAD_NC(GPP_E22, NONE), // NC
PAD_NC(GPP_E23, NONE), // NC
/* ------- GPIO Group F ------- */
PAD_NC(GPP_F0, NONE), // NC
PAD_NC(GPP_F1, NONE), // NC
PAD_NC(GPP_F2, NONE), // NC
PAD_NC(GPP_F3, NONE), // NC
PAD_NC(GPP_F4, NONE), // NC
PAD_NC(GPP_F5, NONE), // NC
PAD_NC(GPP_F6, NONE), // NC
PAD_NC(GPP_F7, NONE), // NC
PAD_NC(GPP_F8, NONE), // NC
PAD_NC(GPP_F9, NONE), // NC
PAD_NC(GPP_F10, NONE), // NC
PAD_NC(GPP_F11, NONE), // NC
PAD_NC(GPP_F12, NONE), // NC
PAD_NC(GPP_F13, NONE), // NC
PAD_NC(GPP_F14, NONE), // NC
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_NC(GPP_F19, NONE), // NC
PAD_NC(GPP_F20, NONE), // NC
PAD_NC(GPP_F21, NONE), // NC
PAD_NC(GPP_F22, NONE), // NC
PAD_NC(GPP_F23, NONE), // LIGHT_KB_DET#
/* ------- GPIO Group G ------- */
PAD_NC(GPP_G0, NONE), // NC
PAD_NC(GPP_G1, NONE), // TBT Detect
PAD_NC(GPP_G2, NONE), // NC
PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
PAD_NC(GPP_G5, NONE), // NC
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // NC
}; };
#endif #endif

View File

@ -10,521 +10,219 @@
/* Early pad configuration in romstage. */ /* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_NC(GPP_C22, NONE), // NC
// UART2_TXD PAD_NC(GPP_C23, NONE), // NC
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management PAD_NC(GPD0, NONE), // PM_BATLOW#
// PM_BATLOW# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_NC(GPD0, NONE), PAD_NC(GPD2, NONE), // NC
// AC_PRESENT PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
// NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD2, NONE), PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
// PWR_BTN# PAD_NC(GPD7, NONE), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
// SUSB#_PCH PAD_NC(GPD9, NONE), // GPD9_RTD3
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
// SUSC#_PCH PAD_NC(GPD11, NONE), // NC
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// SLP_A#
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
// GPIO /* ------- GPIO Group A ------- */
// NC PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_NC(GPD7, NONE), PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with pull up
PAD_NC(GPP_A7, NONE), // TPM_PIRQ#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with pull-up
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_A18, NONE), // NC
PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP), // TEST_R
PAD_NC(GPP_A21, NONE), // NC
PAD_NC(GPP_A22, NONE), // NC
PAD_NC(GPP_A23, NONE), // NC
// Clock Signals /* ------- GPIO Group B ------- */
// SUS_CLK PAD_NC(GPP_B0, NONE), // CORE_VID0
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_NC(GPP_B1, NONE), // CORE_VID1
PAD_NC(GPP_B2, NONE), // CNVI_WAKE#
PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), // GPP_B3 (touchpad interrupt)
PAD_NC(GPP_B4, NONE), // NC
PAD_NC(GPP_B5, NONE), // NC
PAD_NC(GPP_B6, NONE), // NC
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // CARD_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD1_CLKREQ#
PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
PAD_NC(GPP_B23, NONE), // NC
// Power Management /* ------- GPIO Group C ------- */
// GPD9_RTD3 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_NC(GPD9, NONE), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
// NC PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with pull-up
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), PAD_NC(GPP_C3, NONE), // NC
// NC PAD_NC(GPP_C4, NONE), // NC
PAD_NC(GPD11, NONE), PAD_NC(GPP_C5, NONE), // NC
PAD_NC(GPP_C6, NONE), // LAN_WAKEUP#
PAD_NC(GPP_C7, NONE), // NC
PAD_NC(GPP_C8, NONE), // NC
PAD_NC(GPP_C9, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
PAD_NC(GPP_C11, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBTA_HRESET
PAD_NC(GPP_C15, NONE), // NC
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
PAD_NC(GPP_C18, NONE), // NC
PAD_NC(GPP_C19, NONE), // SWI
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE), // NC
PAD_NC(GPP_C23, NONE), // NC
// GPP_A /* ------- GPIO Group D ------- */
// LPC PAD_NC(GPP_D0, NONE), // NC
// SB_KBCRST# PAD_NC(GPP_D1, NONE), // NC
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), PAD_NC(GPP_D2, NONE), // NC
// LPC_AD0 PAD_NC(GPP_D3, NONE), // NC
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), PAD_NC(GPP_D4, NONE), // NC
// LPC_AD1 PAD_NC(GPP_D5, NONE), // NC
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), PAD_NC(GPP_D6, NONE), // NC
// LPC_AD2 PAD_NC(GPP_D7, NONE), // NC
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // SB_BLON
// LPC_AD3 _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), PAD_NC(GPP_D10, NONE), // NC
// LPC_FRAME# PAD_NC(GPP_D11, NONE), // BOARD_ID
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
// SERIRQ with pull up PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST), // GPP_D13_RTD3
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST), // SSD2_PWR_DN#
PAD_NC(GPP_D15, NONE), // NC
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // RTD3_3G_PW R_EN
PAD_NC(GPP_D17, NONE), // NC
PAD_NC(GPP_D18, NONE), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
PAD_NC(GPP_D21, NONE), // TPM_DET#
PAD_NC(GPP_D22, NONE), // TPM_TCM_Detect
PAD_NC(GPP_D23, NONE), // NC
// GSPI0 /* ------- GPIO Group E ------- */
// TPM_PIRQ# PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with pull-up
PAD_NC(GPP_A7, NONE), PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
PAD_NC(GPP_E3, NONE), // NC
PAD_NC(GPP_E4, NONE), // NC
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // DEVSLP1
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
PAD_NC(GPP_E7, NONE), // NC
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
PAD_NC(GPP_E10, NONE), // GPP_E10
PAD_NC(GPP_E11, NONE), // GPP_E11
PAD_NC(GPP_E12, NONE), // USB_OC#78
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_NC(GPP_E22, NONE), // NC
PAD_NC(GPP_E23, NONE), // NC
// LPC /* ------- GPIO Group F ------- */
// PM_CLKRUN# with pull-up PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_NC(GPP_F1, NONE), // NC
// PCLK_KBC PAD_NC(GPP_F2, NONE), // NC
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), PAD_NC(GPP_F3, NONE), // NC
// NC PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_F10, NONE), // NC
PAD_NC(GPP_F11, NONE), // NC
PAD_NC(GPP_F12, NONE), // NC
PAD_NC(GPP_F13, NONE), // NC
PAD_NC(GPP_F14, NONE), // NC
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_NC(GPP_F19, NONE), // NC
PAD_NC(GPP_F20, NONE), // NC
PAD_NC(GPP_F21, NONE), // NC
PAD_NC(GPP_F22, NONE), // NC
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // A4WP_PRESENT
// GSPI1 /* ------- GPIO Group G ------- */
// INTP_OUT PAD_NC(GPP_G0, NONE), // EDP_DET
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), PAD_NC(GPP_G1, NONE), // NC
PAD_NC(GPP_G2, NONE), // NC
PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
PAD_NC(GPP_G5, NONE), // BOARD_ID
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // TBT_Detect
// ISH_GP /* ------- GPIO Group H ------- */
// PCH_GPP_A12 PAD_NC(GPP_H0, NONE), // NC
PAD_NC(GPP_A12, NONE), PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
// Power Management PAD_NC(GPP_H3, NONE), // NC
// SUSWARN# PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SMD_7411
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SMC_7411
PAD_NC(GPP_H6, NONE), // NC
// LPC PAD_NC(GPP_H7, NONE), // NC
// NC PAD_NC(GPP_H8, NONE), // NC
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), PAD_NC(GPP_H9, NONE), // NC
PAD_NC(GPP_H10, NONE), // NC
// Power Management PAD_NC(GPP_H11, NONE), // NC
// SUS_PWR_ACK PAD_NC(GPP_H12, NONE), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_NC(GPP_H13, NONE), // NC
PAD_NC(GPP_H14, NONE), // G_INT1
// SD PAD_NC(GPP_H15, NONE), // NC
// NC PAD_NC(GPP_H16, NONE), // NC
PAD_NC(GPP_A16, NONE), PAD_NC(GPP_H17, NONE), // NC
// LIGHT_KB_DET# PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_A17, NONE), PAD_NC(GPP_H19, NONE), // NC
PAD_NC(GPP_H20, NONE), // NC
// ISH_GP PAD_NC(GPP_H21, NONE), // GPPC_H21
// NC PAD_NC(GPP_H22, NONE), // TBT_RTD3_PWR_EN_R
PAD_NC(GPP_A18, NONE), PAD_NC(GPP_H23, NONE), // NC, WIGIG_PEWAKE
// SATA_PWR_EN
PAD_CFG_GPO(GPP_A19, 1, DEEP),
// TEST_R
PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP),
// NC
PAD_NC(GPP_A21, NONE),
// NC
PAD_NC(GPP_A22, NONE),
// NC
PAD_NC(GPP_A23, NONE),
// GPP_B
// Power
// CORE_VID0
PAD_NC(GPP_B0, NONE),
// CORE_VID1
PAD_NC(GPP_B1, NONE),
// Power Management
// CNVI_WAKE#
PAD_NC(GPP_B2, NONE),
// CPU Misc
// GPP_B3 (touchpad interrupt)
PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),
// NC
PAD_NC(GPP_B4, NONE),
// Clock Signals
// NC
PAD_NC(GPP_B5, NONE),
// NC
PAD_NC(GPP_B6, NONE),
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
// CARD_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
// SSD2_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
// SSD1_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
// Power Management
// EXT_PWR_GATE#
PAD_NC(GPP_B11, NONE),
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// SPKR
// PCH_SPKR
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
// GSPI0
// NC
PAD_NC(GPP_B15, NONE),
// PCH_GPP_B16
PAD_NC(GPP_B16, NONE),
// PCH_GPP_B17
PAD_NC(GPP_B17, NONE),
// PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B18, NONE),
// GSPI1
// NC
PAD_NC(GPP_B19, NONE),
// NC
PAD_NC(GPP_B20, NONE),
// NC
PAD_NC(GPP_B21, NONE),
// PCH_GPP_B22
PAD_NC(GPP_B22, NONE),
// SMBUS
// NC
PAD_NC(GPP_B23, NONE),
// GPP_C
// SMBUS
// SMB_CLK_DDR
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DAT_DDR
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// PCH_GPP_C2 with pull-up
PAD_NC(GPP_C2, NONE),
// NC
PAD_NC(GPP_C3, NONE),
// NC
PAD_NC(GPP_C4, NONE),
// NC
PAD_NC(GPP_C5, NONE),
// LAN_WAKEUP#
PAD_NC(GPP_C6, NONE),
// NC
PAD_NC(GPP_C7, NONE),
// UART0
// NC
PAD_NC(GPP_C8, NONE),
// NC
PAD_NC(GPP_C9, NONE),
// TBT_FRC_PWR
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
// NC
PAD_NC(GPP_C11, NONE),
// UART1
// GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
// SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
// TBTA_HRESET
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
// NC
PAD_NC(GPP_C15, NONE),
// I2C
// T_SDA
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
// T_SCL
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C18, NONE),
// SWI
PAD_NC(GPP_C19, NONE),
// UART2
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
// GPP_D
// SPI1
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_D4, NONE),
// I2C
// NC
PAD_NC(GPP_D5, NONE),
// NC
PAD_NC(GPP_D6, NONE),
// NC
PAD_NC(GPP_D7, NONE),
// SB_BLON
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
// GSPI2
// SWI#
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
// NC
PAD_NC(GPP_D10, NONE),
// BOARD_ID
PAD_NC(GPP_D11, NONE),
// PCH_GPP_D12
PAD_NC(GPP_D12, NONE),
// UART0
// GPP_D13_RTD3
PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
// SSD2_PWR_DN#
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
// NC
PAD_NC(GPP_D15, NONE),
// RTD3_3G_PW R_EN
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
// DMIC
// NC
PAD_NC(GPP_D17, NONE),
// NC
PAD_NC(GPP_D18, NONE),
// GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
// GPPC_DMIC_DATA
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
// SPI1
// TPM_DET#
PAD_NC(GPP_D21, NONE),
// TPM_TCM_Detect
PAD_NC(GPP_D22, NONE),
// I2S
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// PCH_GPP_E0 with pull-up
PAD_NC(GPP_E0, NONE),
// SATAGP1
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
// SATAGP2
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E3, NONE),
// DEVSLP
// NC
PAD_NC(GPP_E4, NONE),
// DEVSLP1
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
// DEVSLP2
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E7, NONE),
// SATA
// PCH_SATAHDD_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB2
// GP_BSSB_CLK
PAD_NC(GPP_E9, NONE),
// GPP_E10
PAD_NC(GPP_E10, NONE),
// GPP_E11
PAD_NC(GPP_E11, NONE),
// USB_OC#78
PAD_NC(GPP_E12, NONE),
// Display Signals
// MUX_HPD
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
// HDMI_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
// SMI#
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
// SCI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
// EDP_HPD
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
// MDP_CTRLCLK
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
// MDP_CTRLDATA
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_E22, NONE),
// NC
PAD_NC(GPP_E23, NONE),
// GPP_F
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
// CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
// CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F10, NONE),
// EMMC
// NC
PAD_NC(GPP_F11, NONE),
// NC
PAD_NC(GPP_F12, NONE),
// NC
PAD_NC(GPP_F13, NONE),
// NC
PAD_NC(GPP_F14, NONE),
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// NC
PAD_NC(GPP_F19, NONE),
// NC
PAD_NC(GPP_F20, NONE),
// NC
PAD_NC(GPP_F21, NONE),
// NC
PAD_NC(GPP_F22, NONE),
// A4WP
// A4WP_PRESENT
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
// GPP_G
// SD
// EDP_DET
PAD_NC(GPP_G0, NONE),
// NC
PAD_NC(GPP_G1, NONE),
// NC
PAD_NC(GPP_G2, NONE),
// ASM1543_I_SEL0
PAD_NC(GPP_G3, NONE),
// ASM1543_I_SEL1
PAD_NC(GPP_G4, NONE),
// BOARD_ID
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// TBT_Detect
PAD_NC(GPP_G7, NONE),
// GPP_H
// CNVI
// NC
PAD_NC(GPP_H0, NONE),
// CNVI_RST#
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
// CNVI_CLKREQ
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
// NC
PAD_NC(GPP_H3, NONE),
// I2C
// SMD_7411
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
// SMC_7411
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_H6, NONE),
// NC
PAD_NC(GPP_H7, NONE),
// NC
PAD_NC(GPP_H8, NONE),
// NC
PAD_NC(GPP_H9, NONE),
// I2C
// NC
PAD_NC(GPP_H10, NONE),
// NC
PAD_NC(GPP_H11, NONE),
// PCIE
// NC
PAD_NC(GPP_H12, NONE),
// NC
PAD_NC(GPP_H13, NONE),
// G_INT1
PAD_NC(GPP_H14, NONE),
// NC
PAD_NC(GPP_H15, NONE),
// Display Signals
// NC
PAD_NC(GPP_H16, NONE),
// NC
PAD_NC(GPP_H17, NONE),
// CPU Power
// CPU_C10_GATE#
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
// TIMESYNC
// NC
PAD_NC(GPP_H19, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_H20, NONE),
// GPIO
// GPPC_H21
PAD_NC(GPP_H21, NONE),
// TBT_RTD3_PWR_EN_R
PAD_NC(GPP_H22, NONE),
// NC, WIGIG_PEWAKE
PAD_NC(GPP_H23, NONE),
}; };
#endif #endif

View File

@ -10,583 +10,257 @@
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management _PAD_CFG_STRUCT(GPD0, 0x4000600, 0x0), // N_-BATLOW
// N_-BATLOW _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x3c00), // N_GP_D1
_PAD_CFG_STRUCT(GPD0, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPD2, 0x80500, 0x3c00), // N_-LAN_WAKE
// N_GP_D1 _PAD_CFG_STRUCT(GPD3, 0x4000500, 0x3000), // O_PWRBTSW
_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x3c00), _PAD_CFG_STRUCT(GPD4, 0x4000600, 0x0), // N_-SLP_S3
// N_-LAN_WAKE _PAD_CFG_STRUCT(GPD5, 0x4000600, 0x0), // N_-S4_S5
_PAD_CFG_STRUCT(GPD2, 0x80500, 0x3c00), _PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0), // N_-SLP_A
// O_PWRBTSW _PAD_CFG_STRUCT(GPD7, 0x4000200, 0x0), // N_GPD_7
_PAD_CFG_STRUCT(GPD3, 0x4000500, 0x3000), _PAD_CFG_STRUCT(GPD8, 0x4000600, 0x0), // N_SUSCLK
// N_-SLP_S3 _PAD_CFG_STRUCT(GPD9, 0x4000600, 0x0), // NC
_PAD_CFG_STRUCT(GPD4, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPD10, 0x4000600, 0x0), // N_-SLP_S5
// N_-S4_S5 _PAD_CFG_STRUCT(GPD11, 0x4000600, 0x0), // N_-LAN_DIS
_PAD_CFG_STRUCT(GPD5, 0x4000600, 0x0),
// N_-SLP_A
_PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0),
// GPIO /* ------- GPIO Group A ------- */
// N_GPD_7 _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), // N_-KBRST
_PAD_CFG_STRUCT(GPD7, 0x4000200, 0x0), _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), // N_LAD0
_PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), // N_LAD1
_PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), // N_LAD2
_PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), // N_LAD3
_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), // N_-LFRAME
_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), // N_SERIRQ
_PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x0), // N_-LDRQ0
_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), // N_GPP_A8
_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), // T_TPMCLK
_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), // N_LPC24MA
_PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x3000), // NC
_PAD_CFG_STRUCT(GPP_A12, 0x44000300, 0x0), // N_GPP_A12
_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), // N_-S_WARN
_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), // N_GPP_A14
_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), // N_-S_ACK
_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x0), // N_GPP_A16
_PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A18, 0x84000201, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A19, 0x84000201, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A20, 0x84000201, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A21, 0x84000201, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x0), // NC
// Power Management /* ------- GPIO Group B ------- */
// N_SUSCLK _PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0), // N_-DDR_V_SEL
_PAD_CFG_STRUCT(GPD8, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x0), // NTP104
// NC _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), // N_-VRALERT
_PAD_CFG_STRUCT(GPD9, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x0), // N_GPP_B3
// N_-SLP_S5 _PAD_CFG_STRUCT(GPP_B4, 0x84000101, 0x0), // N_GPP_B4
_PAD_CFG_STRUCT(GPD10, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPP_B5, 0x84000101, 0x0), // -PCIEX16_PR
// N_-LAN_DIS _PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0), // N_GPP_B6
_PAD_CFG_STRUCT(GPD11, 0x4000600, 0x0), _PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0), // N_GPP_B7
_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), // M2Q_-CLKREQ
_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), // N_GPP_B9
_PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), // M2P_-CLKREQ
_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), // NTP106
_PAD_CFG_STRUCT(GPP_B12, 0x4000100, 0x0), // N_-SLP_S0
_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), // N_-PFMRST
_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0), // N_SPKR
_PAD_CFG_STRUCT(GPP_B15, 0x44000600, 0x0), // N_GPP_B15
_PAD_CFG_STRUCT(GPP_B16, 0x84000101, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B17, 0x84000101, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B18, 0x84000101, 0x0), // N_GPP_B18
_PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B20, 0x4000100, 0x0), // N_GPP_B20
_PAD_CFG_STRUCT(GPP_B21, 0x82000301, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B22, 0x84000101, 0x0), // N_GPP_B22
_PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), // N_-PCH_HOT
// GPP_A /* ------- GPIO Group C ------- */
// LPC _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), // N_SMBCLK
// N_-KBRST _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0), // N_SMBDATA
_PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_C2, 0x44000200, 0x0), // N_-LPCPME
// N_LAD0 _PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x0), // N_SML0CLK
_PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), _PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x0), // N_SML0DAT
// N_LAD1 _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), // N_GPP_C5
_PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), _PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0), // N_SML1CLK
// N_LAD2 _PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0), // N_SML1DAT
_PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), _PAD_CFG_STRUCT(GPP_C8, 0x44000300, 0x0), // N_GPP_C8
// N_LAD3 _PAD_CFG_STRUCT(GPP_C9, 0x44000300, 0x0), // N_GPP_C9
_PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), _PAD_CFG_STRUCT(GPP_C10, 0x44000300, 0x0), // NC
// N_-LFRAME _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x0), // NC
// N_SERIRQ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x0), // NC
// N_-LDRQ0 _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x0), // NTP127
// N_GPP_A8 _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x0), // NTP126
_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x0), // NC
// T_TPMCLK _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0), // NC
// N_LPC24MA _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0), // N_GPP_C21
_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), _PAD_CFG_STRUCT(GPP_C22, 0x44000300, 0x0), // N_GPP_C22
_PAD_CFG_STRUCT(GPP_C23, 0x44000300, 0x0), // N_GPP_C23
// Power Management /* ------- GPIO Group D ------- */
// NC _PAD_CFG_STRUCT(GPP_D0, 0x84000200, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x3000), _PAD_CFG_STRUCT(GPP_D1, 0x84000200, 0x0), // NC
// N_GPP_A12 _PAD_CFG_STRUCT(GPP_D2, 0x84000200, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A12, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x0), // NC
// N_-S_WARN _PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0), // N_GPP_D_4
_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_D5, 0x44000f00, 0x0), // -CNVI_RF_RESET
_PAD_CFG_STRUCT(GPP_D6, 0x44000f00, 0x0), // CNVI_CLKREQ
_PAD_CFG_STRUCT(GPP_D7, 0x44000f00, 0x0), // CNVI_PCM_IN
_PAD_CFG_STRUCT(GPP_D8, 0x44000f00, 0x0), // -CNVI_PCM_CLK
_PAD_CFG_STRUCT(GPP_D9, 0x84000200, 0x0), // N_GPP_D9
_PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x0), // N_GPP_D10
_PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x0), // N_GPP_D11
_PAD_CFG_STRUCT(GPP_D12, 0x44001700, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D19, 0x4000200, 0x0), // N_GPP_D19
_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x0), // N_GPP_D20
_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0), // N_GPP_D21
_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0), // N_GPP_D23
// LPC /* ------- GPIO Group E ------- */
// N_GPP_A14 _PAD_CFG_STRUCT(GPP_E0, 0x84000500, 0x3000), // N_GPP_E0
_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_E1, 0x84000500, 0x3000), // N_GPP_E1
_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x3000), // N_GPP_E2
_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_E4, 0x44000500, 0x0), // N_DEVSLP0
_PAD_CFG_STRUCT(GPP_E5, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_E6, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), // N_-SATALED
_PAD_CFG_STRUCT(GPP_E9, 0x44000500, 0x0), // N_-USBOC_R
_PAD_CFG_STRUCT(GPP_E10, 0x44000500, 0x0), // N_-USBOC_F
_PAD_CFG_STRUCT(GPP_E11, 0x44000500, 0x0), // N_-USBOC_F
_PAD_CFG_STRUCT(GPP_E12, 0x44000500, 0x0), // N_-USBOC_R
// Power Management /* ------- GPIO Group F ------- */
// N_-S_ACK _PAD_CFG_STRUCT(GPP_F0, 0x84000500, 0x3000), // N_GPP_F0
_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), _PAD_CFG_STRUCT(GPP_F1, 0x84000500, 0x3000), // N_GPP_F1
_PAD_CFG_STRUCT(GPP_F2, 0x84000500, 0x3000), // N_GPP_F2
_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), // N_GPP_F3
_PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x0), // N_GPP_F4
_PAD_CFG_STRUCT(GPP_F5, 0x44000500, 0x0), // N_GPP_F5
_PAD_CFG_STRUCT(GPP_F6, 0x44000500, 0x0), // N_DEVSLP4
_PAD_CFG_STRUCT(GPP_F7, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_F8, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_F9, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_F10, 0x84000100, 0x0), // N_GPP_F10
_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0), // N_GPP_F11
_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0), // N_GPP_F12
_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0), // N_GPP_F13
_PAD_CFG_STRUCT(GPP_F14, 0x44000b00, 0x0), // NTP124
_PAD_CFG_STRUCT(GPP_F15, 0x44000500, 0x0), // N_-USBOC_F
_PAD_CFG_STRUCT(GPP_F16, 0x44000500, 0x0), // N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F17, 0x44000500, 0x0), // N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F18, 0x44000500, 0x0), // N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), // NC
_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), // NTP88
_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), // NTP87
_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0), // N_GPP_F22
_PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x0), // N_GPP_F23
// Clock Signals /* ------- GPIO Group G ------- */
// N_GPP_A16 _PAD_CFG_STRUCT(GPP_G0, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_G1, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_G2, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_G3, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x0), // N_GPPC_G6
_PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x0), // NC
// ISH /* ------- GPIO Group H ------- */
// NC _PAD_CFG_STRUCT(GPP_H0, 0x44000700, 0x0), // LB_-CLKREQ
_PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0), _PAD_CFG_STRUCT(GPP_H1, 0x44000100, 0x0), // N_GPP_H1
// NC _PAD_CFG_STRUCT(GPP_H2, 0x44000300, 0x0), // N_GPP_H2
_PAD_CFG_STRUCT(GPP_A18, 0x84000201, 0x0), _PAD_CFG_STRUCT(GPP_H3, 0x44000300, 0x0), // N_GPP_H3
// NC _PAD_CFG_STRUCT(GPP_H4, 0x44000300, 0x0), // N_GPP_H4
_PAD_CFG_STRUCT(GPP_A19, 0x84000201, 0x0), _PAD_CFG_STRUCT(GPP_H5, 0x44000300, 0x0), // N_GPP_H5
// NC _PAD_CFG_STRUCT(GPP_H6, 0x44000300, 0x0), // N_GPP_H6
_PAD_CFG_STRUCT(GPP_A20, 0x84000201, 0x0), _PAD_CFG_STRUCT(GPP_H7, 0x44000300, 0x0), // N_GPP_H7
// NC _PAD_CFG_STRUCT(GPP_H8, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A21, 0x84000201, 0x0), _PAD_CFG_STRUCT(GPP_H9, 0x44000300, 0x0), // NC
// NC _PAD_CFG_STRUCT(GPP_H10, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_H11, 0x44000300, 0x0), // NC
// NC _PAD_CFG_STRUCT(GPP_H12, 0x44000200, 0x0), // N_GPP_H12
_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_H13, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_H14, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x0), // N_GPP_H15
_PAD_CFG_STRUCT(GPP_H16, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_H17, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_H19, 0x44000300, 0x0), // N_GPP_H19
_PAD_CFG_STRUCT(GPP_H20, 0x44000300, 0x0), // N_GPP_H20
_PAD_CFG_STRUCT(GPP_H21, 0x44000300, 0x0), // N_GPP_H21
_PAD_CFG_STRUCT(GPP_H22, 0x44000300, 0x0), // N_GPP_H22
_PAD_CFG_STRUCT(GPP_H23, 0x44000300, 0x0), // NC
// GPP_B /* ------- GPIO Group I ------- */
// GSPI _PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00), // N_HDMI_HDP_F
// N_-DDR_V_SEL _PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00), // N_HDMI20_HDP_F
_PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0), _PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00), // DP_HDP
// NTP104 _PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0), // N_GPP_I3
_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0), // N_GPP_I4
_PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0), // N_DDPB_CTRLCLK
_PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0), // N_DDPB_CTRLDATA
_PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0), // N_DDPC_CTRLCLK
_PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0), // N_DDPC_CTRLDATA
_PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000), // N_DDPD_CTRLCLK
_PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000), // N_DDPD_CTRLDATA
_PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00), // A_-SKTOCC
_PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00), // NC
_PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00), // NC
_PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00), // NC
// Power Management /* ------- GPIO Group J ------- */
// N_-VRALERT _PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00), // CNVI_PA_BLANKING
_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00), // CPU_VCCIO_PW R_GATEB
_PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00), // NC
_PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00), // NC
_PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00), // CNVI_BRI_DT
_PAD_CFG_STRUCT(GPP_J5, 0x44000500, 0x0), // CNVI_BRI_RSP
_PAD_CFG_STRUCT(GPP_J6, 0x44000500, 0x0), // CNVI_RGI_DT
_PAD_CFG_STRUCT(GPP_J7, 0x44000500, 0x0), // CNVI_RGI_RSP
_PAD_CFG_STRUCT(GPP_J8, 0x44000500, 0x0), // CNVI_MFUART2_RXD
_PAD_CFG_STRUCT(GPP_J9, 0x44000500, 0x0), // CNVI_MFUART2_TXD
_PAD_CFG_STRUCT(GPP_J10, 0x44000500, 0x0), // NC
_PAD_CFG_STRUCT(GPP_J11, 0x44000600, 0x0), // NTP122
// CPU Misc /* ------- GPIO Group K ------- */
// N_GPP_B3 _PAD_CFG_STRUCT(GPP_K0, 0x4000100, 0x0), // N_GPP_K0
_PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_K1, 0x4000100, 0x0), // N_GPP_K1
// N_GPP_B4 _PAD_CFG_STRUCT(GPP_K2, 0x44000300, 0x0), // N_GPP_K2
_PAD_CFG_STRUCT(GPP_B4, 0x84000101, 0x0), _PAD_CFG_STRUCT(GPP_K3, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_K4, 0x44000300, 0x0), // NC
// Clock Signals _PAD_CFG_STRUCT(GPP_K5, 0x44000300, 0x0), // NC
// -PCIEX16_PR _PAD_CFG_STRUCT(GPP_K6, 0x44000300, 0x0), // N_GPP_K6
_PAD_CFG_STRUCT(GPP_B5, 0x84000101, 0x0), _PAD_CFG_STRUCT(GPP_K7, 0x44000300, 0x0), // NC
// N_GPP_B6 _PAD_CFG_STRUCT(GPP_K8, 0x44000700, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_K9, 0x44000700, 0x0), // NC
// N_GPP_B7 _PAD_CFG_STRUCT(GPP_K10, 0x44000700, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_K11, 0x44000700, 0x0), // NC
// M2Q_-CLKREQ _PAD_CFG_STRUCT(GPP_K12, 0x44000300, 0x0), // NC
_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_K13, 0x44000300, 0x0), // NC
// N_GPP_B9 _PAD_CFG_STRUCT(GPP_K14, 0x44000300, 0x0), // N_GT_S
_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_K15, 0x44000300, 0x0), // N_CPU_S
// M2P_-CLKREQ _PAD_CFG_STRUCT(GPP_K16, 0x44000300, 0x0), // M2_BT_DISABLE
_PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), _PAD_CFG_STRUCT(GPP_K17, 0x44000300, 0x0), // M2_WIFI_DISABLE
_PAD_CFG_STRUCT(GPP_K18, 0x44000300, 0x0), // N_GPP_K18
// Audio _PAD_CFG_STRUCT(GPP_K19, 0x44000300, 0x0), // N_GPP_K19
// NTP106 _PAD_CFG_STRUCT(GPP_K20, 0x44000700, 0x0), // N_GPP_K20
_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), _PAD_CFG_STRUCT(GPP_K21, 0x44000700, 0x0), // N_GPP_K21
_PAD_CFG_STRUCT(GPP_K22, 0x44000300, 0x0), // N_GPP_K22
// Power Management _PAD_CFG_STRUCT(GPP_K23, 0x44000300, 0x0), // NC
// N_-SLP_S0
_PAD_CFG_STRUCT(GPP_B12, 0x4000100, 0x0),
// N_-PFMRST
_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
// Audio
// N_SPKR
_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0),
// GSPI
// N_GPP_B15
_PAD_CFG_STRUCT(GPP_B15, 0x44000600, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_B16, 0x84000101, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_B17, 0x84000101, 0x0),
// N_GPP_B18
_PAD_CFG_STRUCT(GPP_B18, 0x84000101, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0),
// N_GPP_B20
_PAD_CFG_STRUCT(GPP_B20, 0x4000100, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_B21, 0x82000301, 0x0),
// N_GPP_B22
_PAD_CFG_STRUCT(GPP_B22, 0x84000101, 0x0),
// SMBUS
// N_-PCH_HOT
_PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0),
// GPP_C
// SMBUS
// N_SMBCLK
_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0),
// N_SMBDATA
_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0),
// N_-LPCPME
_PAD_CFG_STRUCT(GPP_C2, 0x44000200, 0x0),
// N_SML0CLK
_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x0),
// N_SML0DAT
_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x0),
// N_GPP_C5
_PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0),
// N_SML1CLK
_PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0),
// N_SML1DAT
_PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0),
// UART
// N_GPP_C8
_PAD_CFG_STRUCT(GPP_C8, 0x44000300, 0x0),
// N_GPP_C9
_PAD_CFG_STRUCT(GPP_C9, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C10, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x0),
// I2C
// NTP127
_PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x0),
// NTP126
_PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x0),
// UART
// NC
_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0),
// N_GPP_C21
_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0),
// N_GPP_C22
_PAD_CFG_STRUCT(GPP_C22, 0x44000300, 0x0),
// N_GPP_C23
_PAD_CFG_STRUCT(GPP_C23, 0x44000300, 0x0),
// GPP_D
// SPI
// NC
_PAD_CFG_STRUCT(GPP_D0, 0x84000200, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D1, 0x84000200, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D2, 0x84000200, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x0),
// I2C
// N_GPP_D_4
_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0),
// CNVI
// -CNVI_RF_RESET
_PAD_CFG_STRUCT(GPP_D5, 0x44000f00, 0x0),
// CNVI_CLKREQ
_PAD_CFG_STRUCT(GPP_D6, 0x44000f00, 0x0),
// CNVI_PCM_IN
_PAD_CFG_STRUCT(GPP_D7, 0x44000f00, 0x0),
// -CNVI_PCM_CLK
_PAD_CFG_STRUCT(GPP_D8, 0x44000f00, 0x0),
// ISH
// N_GPP_D9
_PAD_CFG_STRUCT(GPP_D9, 0x84000200, 0x0),
// N_GPP_D10
_PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x0),
// N_GPP_D11
_PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D12, 0x44001700, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x0),
// DMIC
// NC
_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x0),
// N_GPP_D19
_PAD_CFG_STRUCT(GPP_D19, 0x4000200, 0x0),
// N_GPP_D20
_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x0),
// SPI
// N_GPP_D21
_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0),
// ISH
// N_GPP_D23
_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0),
// GPP_E
// SATA
// N_GPP_E0
_PAD_CFG_STRUCT(GPP_E0, 0x84000500, 0x3000),
// N_GPP_E1
_PAD_CFG_STRUCT(GPP_E1, 0x84000500, 0x3000),
// N_GPP_E2
_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x3000),
// CPU Misc
// NC
_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x0),
// SATA
// N_DEVSLP0
_PAD_CFG_STRUCT(GPP_E4, 0x44000500, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_E5, 0x44000500, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_E6, 0x44000500, 0x0),
// CPU Misc
// NC
_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0),
// SATA
// N_-SATALED
_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
// USB2
// N_-USBOC_R
_PAD_CFG_STRUCT(GPP_E9, 0x44000500, 0x0),
// N_-USBOC_F
_PAD_CFG_STRUCT(GPP_E10, 0x44000500, 0x0),
// N_-USBOC_F
_PAD_CFG_STRUCT(GPP_E11, 0x44000500, 0x0),
// N_-USBOC_R
_PAD_CFG_STRUCT(GPP_E12, 0x44000500, 0x0),
// GPP_F
// SATA
// N_GPP_F0
_PAD_CFG_STRUCT(GPP_F0, 0x84000500, 0x3000),
// N_GPP_F1
_PAD_CFG_STRUCT(GPP_F1, 0x84000500, 0x3000),
// N_GPP_F2
_PAD_CFG_STRUCT(GPP_F2, 0x84000500, 0x3000),
// N_GPP_F3
_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0),
// N_GPP_F4
_PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x0),
// N_GPP_F5
_PAD_CFG_STRUCT(GPP_F5, 0x44000500, 0x0),
// N_DEVSLP4
_PAD_CFG_STRUCT(GPP_F6, 0x44000500, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_F7, 0x44000500, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_F8, 0x44000500, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_F9, 0x44000500, 0x0),
// N_GPP_F10
_PAD_CFG_STRUCT(GPP_F10, 0x84000100, 0x0),
// N_GPP_F11
_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0),
// N_GPP_F12
_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0),
// N_GPP_F13
_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0),
// Power Management
// NTP124
_PAD_CFG_STRUCT(GPP_F14, 0x44000b00, 0x0),
// USB2
// N_-USBOC_F
_PAD_CFG_STRUCT(GPP_F15, 0x44000500, 0x0),
// N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F16, 0x44000500, 0x0),
// N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F17, 0x44000500, 0x0),
// N_-USBOC_7
_PAD_CFG_STRUCT(GPP_F18, 0x44000500, 0x0),
// Display Signals
// NC
_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0),
// NTP88
_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0),
// NTP87
_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
// N_GPP_F22
_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0),
// N_GPP_F23
_PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x0),
// GPP_G
// SD
// NC
_PAD_CFG_STRUCT(GPP_G0, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G1, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G2, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G3, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x0),
// N_GPPC_G6
_PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x0),
// GPP_H
// Clock Signals
// LB_-CLKREQ
_PAD_CFG_STRUCT(GPP_H0, 0x44000700, 0x0),
// N_GPP_H1
_PAD_CFG_STRUCT(GPP_H1, 0x44000100, 0x0),
// N_GPP_H2
_PAD_CFG_STRUCT(GPP_H2, 0x44000300, 0x0),
// N_GPP_H3
_PAD_CFG_STRUCT(GPP_H3, 0x44000300, 0x0),
// N_GPP_H4
_PAD_CFG_STRUCT(GPP_H4, 0x44000300, 0x0),
// N_GPP_H5
_PAD_CFG_STRUCT(GPP_H5, 0x44000300, 0x0),
// N_GPP_H6
_PAD_CFG_STRUCT(GPP_H6, 0x44000300, 0x0),
// N_GPP_H7
_PAD_CFG_STRUCT(GPP_H7, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H8, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H9, 0x44000300, 0x0),
// SMBUS
// NC
_PAD_CFG_STRUCT(GPP_H10, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H11, 0x44000300, 0x0),
// N_GPP_H12
_PAD_CFG_STRUCT(GPP_H12, 0x44000200, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H13, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H14, 0x44000300, 0x0),
// N_GPP_H15
_PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H16, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H17, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x0),
// ISH
// N_GPP_H19
_PAD_CFG_STRUCT(GPP_H19, 0x44000300, 0x0),
// N_GPP_H20
_PAD_CFG_STRUCT(GPP_H20, 0x44000300, 0x0),
// N_GPP_H21
_PAD_CFG_STRUCT(GPP_H21, 0x44000300, 0x0),
// N_GPP_H22
_PAD_CFG_STRUCT(GPP_H22, 0x44000300, 0x0),
// GPIO
// NC
_PAD_CFG_STRUCT(GPP_H23, 0x44000300, 0x0),
// GPP_I
// Display Signals
// N_HDMI_HDP_F
_PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00),
// N_HDMI20_HDP_F
_PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00),
// DP_HDP
_PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00),
// N_GPP_I3
_PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0),
// N_GPP_I4
_PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0),
// N_DDPB_CTRLCLK
_PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0),
// N_DDPB_CTRLDATA
_PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0),
// N_DDPC_CTRLCLK
_PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0),
// N_DDPC_CTRLDATA
_PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0),
// N_DDPD_CTRLCLK
_PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000),
// N_DDPD_CTRLDATA
_PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000),
// PCIE
// A_-SKTOCC
_PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00),
// NC
_PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00),
// NC
_PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00),
// NC
_PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00),
// GPP_J
// CNVI
// CNVI_PA_BLANKING
_PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00),
// Power Management
// CPU_VCCIO_PW R_GATEB
_PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00),
// GPIO
// NC
_PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00),
// NC
_PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00),
// CNVI
// CNVI_BRI_DT
_PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00),
// CNVI_BRI_RSP
_PAD_CFG_STRUCT(GPP_J5, 0x44000500, 0x0),
// CNVI_RGI_DT
_PAD_CFG_STRUCT(GPP_J6, 0x44000500, 0x0),
// CNVI_RGI_RSP
_PAD_CFG_STRUCT(GPP_J7, 0x44000500, 0x0),
// CNVI_MFUART2_RXD
_PAD_CFG_STRUCT(GPP_J8, 0x44000500, 0x0),
// CNVI_MFUART2_TXD
_PAD_CFG_STRUCT(GPP_J9, 0x44000500, 0x0),
// GPIO
// NC
_PAD_CFG_STRUCT(GPP_J10, 0x44000500, 0x0),
// A4WP
// NTP122
_PAD_CFG_STRUCT(GPP_J11, 0x44000600, 0x0),
// GPP_K
// GPIO
// N_GPP_K0
_PAD_CFG_STRUCT(GPP_K0, 0x4000100, 0x0),
// N_GPP_K1
_PAD_CFG_STRUCT(GPP_K1, 0x4000100, 0x0),
// N_GPP_K2
_PAD_CFG_STRUCT(GPP_K2, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K3, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K4, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K5, 0x44000300, 0x0),
// N_GPP_K6
_PAD_CFG_STRUCT(GPP_K6, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K7, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K8, 0x44000700, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K9, 0x44000700, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K10, 0x44000700, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K11, 0x44000700, 0x0),
// GSX
// NC
_PAD_CFG_STRUCT(GPP_K12, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K13, 0x44000300, 0x0),
// N_GT_S
_PAD_CFG_STRUCT(GPP_K14, 0x44000300, 0x0),
// N_CPU_S
_PAD_CFG_STRUCT(GPP_K15, 0x44000300, 0x0),
// M2_BT_DISABLE
_PAD_CFG_STRUCT(GPP_K16, 0x44000300, 0x0),
// GPIO
// M2_WIFI_DISABLE
_PAD_CFG_STRUCT(GPP_K17, 0x44000300, 0x0),
// N_GPP_K18
_PAD_CFG_STRUCT(GPP_K18, 0x44000300, 0x0),
// N_GPP_K19
_PAD_CFG_STRUCT(GPP_K19, 0x44000300, 0x0),
// N_GPP_K20
_PAD_CFG_STRUCT(GPP_K20, 0x44000700, 0x0),
// N_GPP_K21
_PAD_CFG_STRUCT(GPP_K21, 0x44000700, 0x0),
// N_GPP_K22
_PAD_CFG_STRUCT(GPP_K22, 0x44000300, 0x0),
// NC
_PAD_CFG_STRUCT(GPP_K23, 0x44000300, 0x0),
}; };
#endif #endif

View File

@ -10,521 +10,219 @@
/* Early pad configuration in romstage. */ /* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
// UART2_RXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), PAD_NC(GPP_C22, NONE), // NC
// UART2_TXD PAD_NC(GPP_C23, NONE), // NC
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// NC
PAD_NC(GPP_C23, NONE),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
// GPD /* ------- GPIO Group GPD ------- */
// Power Management PAD_NC(GPD0, NONE), // PM_BATLOW#
// PM_BATLOW# PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_NC(GPD0, NONE), PAD_NC(GPD2, NONE), // NC
// AC_PRESENT PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
// NC PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD2, NONE), PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
// PWR_BTN# PAD_NC(GPD7, NONE), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
// SUSB#_PCH PAD_NC(GPD9, NONE), // GPD9_RTD3
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
// SUSC#_PCH PAD_NC(GPD11, NONE), // NC
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// SLP_A#
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
// GPIO /* ------- GPIO Group A ------- */
// NC PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_NC(GPD7, NONE), PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with pull up
PAD_NC(GPP_A7, NONE), // TPM_PIRQ#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with pull-up
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
PAD_NC(GPP_A11, NONE), // NC
PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_A18, NONE), // NC
PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // PS8338B_SW
PAD_NC(GPP_A23, NONE), // PS8338B_PCH
// Clock Signals /* ------- GPIO Group B ------- */
// SUS_CLK PAD_NC(GPP_B0, NONE), // CORE_VID0
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), PAD_NC(GPP_B1, NONE), // CORE_VID1
PAD_NC(GPP_B2, NONE), // CNVI_WAKE#
PAD_NC(GPP_B3, NONE), // NC
PAD_NC(GPP_B4, NONE), // NC
PAD_NC(GPP_B5, NONE), // NC
PAD_NC(GPP_B6, NONE), // NC
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
PAD_NC(GPP_B23, NONE), // NC
// Power Management /* ------- GPIO Group C ------- */
// GPD9_RTD3 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_NC(GPD9, NONE), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
// NC PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with pull-up
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), PAD_NC(GPP_C3, NONE), // NC
// NC PAD_NC(GPP_C4, NONE), // NC
PAD_NC(GPD11, NONE), PAD_NC(GPP_C5, NONE), // NC
PAD_NC(GPP_C6, NONE), // LAN_WAKEUP#
PAD_NC(GPP_C7, NONE), // NC
PAD_NC(GPP_C8, NONE), // NC
_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
PAD_CFG_TERM_GPO(GPP_C10, 1, NONE, PLTRST), // TBT_FRC_PWR
PAD_NC(GPP_C11, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBTA_HRESET
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
PAD_NC(GPP_C18, NONE), // NC
PAD_NC(GPP_C19, NONE), // SWI
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE), // NC
PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
// GPP_A /* ------- GPIO Group D ------- */
// LPC PAD_NC(GPP_D0, NONE), // NC
// SB_KBCRST# PAD_NC(GPP_D1, NONE), // NC
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), PAD_NC(GPP_D2, NONE), // NC
// LPC_AD0 PAD_NC(GPP_D3, NONE), // NC
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), PAD_NC(GPP_D4, NONE), // NC
// LPC_AD1 PAD_NC(GPP_D5, NONE), // NC
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), PAD_NC(GPP_D6, NONE), // NC
// LPC_AD2 PAD_NC(GPP_D7, NONE), // NC
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // SB_BLON
// LPC_AD3 _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), PAD_NC(GPP_D10, NONE), // NC
// LPC_FRAME# _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
// SERIRQ with pull up PAD_NC(GPP_D13, NONE), // NC
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // RTD3_3G_PW R_EN
PAD_NC(GPP_D17, NONE), // NC
PAD_NC(GPP_D18, NONE), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
PAD_NC(GPP_D21, NONE), // TPM_DET#
PAD_NC(GPP_D22, NONE), // TPM_TCM_Detect
PAD_NC(GPP_D23, NONE), // NC
// GSPI0 /* ------- GPIO Group E ------- */
// TPM_PIRQ# PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with pull-up
PAD_NC(GPP_A7, NONE), PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
PAD_NC(GPP_E3, NONE), // NC
PAD_NC(GPP_E4, NONE), // NC
PAD_NC(GPP_E5, NONE), // NC
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
PAD_NC(GPP_E7, NONE), // NC
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
PAD_NC(GPP_E10, NONE), // GPP_E10
PAD_NC(GPP_E11, NONE), // GPP_E11
PAD_NC(GPP_E12, NONE), // USB_OC#78
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_NC(GPP_E22, NONE), // NC
PAD_NC(GPP_E23, NONE), // NC
// LPC /* ------- GPIO Group F ------- */
// PM_CLKRUN# with pull-up PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_NC(GPP_F1, NONE), // NC
// PCLK_KBC PAD_NC(GPP_F2, NONE), // NC
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), PAD_NC(GPP_F3, NONE), // NC
// NC PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_F10, NONE), // NC
PAD_NC(GPP_F11, NONE), // NC
PAD_NC(GPP_F12, NONE), // NC
PAD_NC(GPP_F13, NONE), // NC
PAD_NC(GPP_F14, NONE), // NC
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_NC(GPP_F19, NONE), // NC
PAD_NC(GPP_F20, NONE), // NC
PAD_NC(GPP_F21, NONE), // NC
PAD_NC(GPP_F22, NONE), // NC
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // A4WP_PRESENT
// GSPI1 /* ------- GPIO Group G ------- */
// NC PAD_NC(GPP_G0, NONE), // EDP_DET
PAD_NC(GPP_A11, NONE), PAD_NC(GPP_G1, NONE), // NC
PAD_NC(GPP_G2, NONE), // NC
PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
PAD_NC(GPP_G5, NONE), // BOARD_ID
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // TBT_Detect
// ISH_GP /* ------- GPIO Group H ------- */
// PCH_GPP_A12 PAD_NC(GPP_H0, NONE), // NC
PAD_NC(GPP_A12, NONE), PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
// Power Management PAD_NC(GPP_H3, NONE), // NC
// SUSWARN# PAD_NC(GPP_H4, NONE), // T23
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_NC(GPP_H5, NONE), // T22
PAD_NC(GPP_H6, NONE), // NC
// LPC PAD_NC(GPP_H7, NONE), // NC
// NC PAD_NC(GPP_H8, NONE), // NC
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), PAD_NC(GPP_H9, NONE), // NC
PAD_NC(GPP_H10, NONE), // NC
// Power Management PAD_NC(GPP_H11, NONE), // NC
// SUS_PWR_ACK PAD_NC(GPP_H12, NONE), // NC
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_NC(GPP_H13, NONE), // NC
PAD_NC(GPP_H14, NONE), // G_INT1
// SD PAD_NC(GPP_H15, NONE), // NC
// NC PAD_NC(GPP_H16, NONE), // NC
PAD_NC(GPP_A16, NONE), PAD_NC(GPP_H17, NONE), // NC
// LIGHT_KB_DET# PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_A17, NONE), PAD_NC(GPP_H19, NONE), // NC
PAD_NC(GPP_H20, NONE), // NC
// ISH_GP PAD_NC(GPP_H21, NONE), // GPPC_H21
// NC PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST), // TBT_RTD3_PWR_EN_R
PAD_NC(GPP_A18, NONE), PAD_NC(GPP_H23, NONE), // NC, WIGIG_PEWAKE
// SATA_PWR_EN
PAD_CFG_GPO(GPP_A19, 1, DEEP),
// NC
PAD_NC(GPP_A20, NONE),
// NC
PAD_NC(GPP_A21, NONE),
// PS8338B_SW
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
// PS8338B_PCH
PAD_NC(GPP_A23, NONE),
// GPP_B
// Power
// CORE_VID0
PAD_NC(GPP_B0, NONE),
// CORE_VID1
PAD_NC(GPP_B1, NONE),
// Power Management
// CNVI_WAKE#
PAD_NC(GPP_B2, NONE),
// CPU Misc
// NC
PAD_NC(GPP_B3, NONE),
// NC
PAD_NC(GPP_B4, NONE),
// Clock Signals
// NC
PAD_NC(GPP_B5, NONE),
// NC
PAD_NC(GPP_B6, NONE),
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
// LAN_CLKREQ#
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
// TBT_CLKREQ#
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
// Power Management
// EXT_PWR_GATE#
PAD_NC(GPP_B11, NONE),
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
// SPKR
// PCH_SPKR
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
// GSPI0
// NC
PAD_NC(GPP_B15, NONE),
// PCH_GPP_B16
PAD_NC(GPP_B16, NONE),
// PCH_GPP_B17
PAD_NC(GPP_B17, NONE),
// PCH_GPP_B18 - strap for disabling no reboot mode
PAD_NC(GPP_B18, NONE),
// GSPI1
// NC
PAD_NC(GPP_B19, NONE),
// NC
PAD_NC(GPP_B20, NONE),
// NC
PAD_NC(GPP_B21, NONE),
// PCH_GPP_B22
PAD_NC(GPP_B22, NONE),
// SMBUS
// NC
PAD_NC(GPP_B23, NONE),
// GPP_C
// SMBUS
// SMB_CLK_DDR
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
// SMB_DAT_DDR
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// PCH_GPP_C2 with pull-up
PAD_NC(GPP_C2, NONE),
// NC
PAD_NC(GPP_C3, NONE),
// NC
PAD_NC(GPP_C4, NONE),
// NC
PAD_NC(GPP_C5, NONE),
// LAN_WAKEUP#
PAD_NC(GPP_C6, NONE),
// NC
PAD_NC(GPP_C7, NONE),
// UART0
// NC
PAD_NC(GPP_C8, NONE),
// TBCIO_PLUG_EVENT
_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
// TBT_FRC_PWR
PAD_CFG_TERM_GPO(GPP_C10, 1, NONE, PLTRST),
// NC
PAD_NC(GPP_C11, NONE),
// UART1
// GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
// SSD_PWR_DN#
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
// TBTA_HRESET
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
// TBT_PERST_N
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
// I2C
// T_SDA
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
// T_SCL
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C18, NONE),
// SWI
PAD_NC(GPP_C19, NONE),
// UART2
// UART2_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_C22, NONE),
// TP_ATTN#
PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
// GPP_D
// SPI1
// NC
PAD_NC(GPP_D0, NONE),
// NC
PAD_NC(GPP_D1, NONE),
// NC
PAD_NC(GPP_D2, NONE),
// NC
PAD_NC(GPP_D3, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_D4, NONE),
// I2C
// NC
PAD_NC(GPP_D5, NONE),
// NC
PAD_NC(GPP_D6, NONE),
// NC
PAD_NC(GPP_D7, NONE),
// SB_BLON
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
// GSPI2
// SWI#
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
// NC
PAD_NC(GPP_D10, NONE),
// RTD3_PCIE_WAKE#
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
// PCH_GPP_D12
PAD_NC(GPP_D12, NONE),
// UART0
// NC
PAD_NC(GPP_D13, NONE),
// NC
PAD_NC(GPP_D14, NONE),
// NC
PAD_NC(GPP_D15, NONE),
// RTD3_3G_PW R_EN
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
// DMIC
// NC
PAD_NC(GPP_D17, NONE),
// NC
PAD_NC(GPP_D18, NONE),
// GPPC_DMIC_CLK
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
// GPPC_DMIC_DATA
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
// SPI1
// TPM_DET#
PAD_NC(GPP_D21, NONE),
// TPM_TCM_Detect
PAD_NC(GPP_D22, NONE),
// I2S
// NC
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// PCH_GPP_E0 with pull-up
PAD_NC(GPP_E0, NONE),
// SATA_ODD_PRSNT#
PAD_NC(GPP_E1, NONE),
// SATAGP2
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E3, NONE),
// DEVSLP
// NC
PAD_NC(GPP_E4, NONE),
// NC
PAD_NC(GPP_E5, NONE),
// DEVSLP2
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
// CPU Misc
// NC
PAD_NC(GPP_E7, NONE),
// SATA
// PCH_SATAHDD_LED#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
// USB2
// GP_BSSB_CLK
PAD_NC(GPP_E9, NONE),
// GPP_E10
PAD_NC(GPP_E10, NONE),
// GPP_E11
PAD_NC(GPP_E11, NONE),
// USB_OC#78
PAD_NC(GPP_E12, NONE),
// Display Signals
// MUX_HPD
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
// HDMI_HPD
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
// SMI#
_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
// SCI#
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
// EDP_HPD
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
// MDP_CTRLCLK
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
// MDP_CTRLDATA
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
// NC
PAD_NC(GPP_E22, NONE),
// NC
PAD_NC(GPP_E23, NONE),
// GPP_F
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F1, NONE),
// NC
PAD_NC(GPP_F2, NONE),
// NC
PAD_NC(GPP_F3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
// CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
// CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
// GPIO
// NC
PAD_NC(GPP_F10, NONE),
// EMMC
// NC
PAD_NC(GPP_F11, NONE),
// NC
PAD_NC(GPP_F12, NONE),
// NC
PAD_NC(GPP_F13, NONE),
// NC
PAD_NC(GPP_F14, NONE),
// NC
PAD_NC(GPP_F15, NONE),
// NC
PAD_NC(GPP_F16, NONE),
// NC
PAD_NC(GPP_F17, NONE),
// NC
PAD_NC(GPP_F18, NONE),
// NC
PAD_NC(GPP_F19, NONE),
// NC
PAD_NC(GPP_F20, NONE),
// NC
PAD_NC(GPP_F21, NONE),
// NC
PAD_NC(GPP_F22, NONE),
// A4WP
// A4WP_PRESENT
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
// GPP_G
// SD
// EDP_DET
PAD_NC(GPP_G0, NONE),
// NC
PAD_NC(GPP_G1, NONE),
// NC
PAD_NC(GPP_G2, NONE),
// ASM1543_I_SEL0
PAD_NC(GPP_G3, NONE),
// ASM1543_I_SEL1
PAD_NC(GPP_G4, NONE),
// BOARD_ID
PAD_NC(GPP_G5, NONE),
// NC
PAD_NC(GPP_G6, NONE),
// TBT_Detect
PAD_NC(GPP_G7, NONE),
// GPP_H
// CNVI
// NC
PAD_NC(GPP_H0, NONE),
// CNVI_RST#
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
// CNVI_CLKREQ
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
// NC
PAD_NC(GPP_H3, NONE),
// I2C
// T23
PAD_NC(GPP_H4, NONE),
// T22
PAD_NC(GPP_H5, NONE),
// NC
PAD_NC(GPP_H6, NONE),
// NC
PAD_NC(GPP_H7, NONE),
// NC
PAD_NC(GPP_H8, NONE),
// NC
PAD_NC(GPP_H9, NONE),
// I2C
// NC
PAD_NC(GPP_H10, NONE),
// NC
PAD_NC(GPP_H11, NONE),
// PCIE
// NC
PAD_NC(GPP_H12, NONE),
// NC
PAD_NC(GPP_H13, NONE),
// G_INT1
PAD_NC(GPP_H14, NONE),
// NC
PAD_NC(GPP_H15, NONE),
// Display Signals
// NC
PAD_NC(GPP_H16, NONE),
// NC
PAD_NC(GPP_H17, NONE),
// CPU Power
// CPU_C10_GATE#
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
// TIMESYNC
// NC
PAD_NC(GPP_H19, NONE),
// IMGCLKOUT
// NC
PAD_NC(GPP_H20, NONE),
// GPIO
// GPPC_H21
PAD_NC(GPP_H21, NONE),
// TBT_RTD3_PWR_EN_R
PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST),
// NC, WIGIG_PEWAKE
PAD_NC(GPP_H23, NONE),
}; };
#endif #endif