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superio/fintek/f81216h: Drop support

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No mainboards use this anymore.

Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Keith Hui 2020-05-02 19:19:04 -04:00 committed by Patrick Georgi
parent 07171b480c
commit 296ce46bcc
6 changed files with 0 additions and 216 deletions
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6
src/superio/fintek/f81216h/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
# This file is part of the coreboot project.
config SUPERIO_FINTEK_F81216H
bool
# N.B. 'special romstage'

6
src/superio/fintek/f81216h/Makefile.inc
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# SPDX-License-Identifier: GPL-2.0-or-later
# This file is part of the coreboot project.
bootblock-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c
romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c

23
src/superio/fintek/f81216h/chip.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* This file is part of the coreboot project. */
#ifndef SUPERIO_FINTEK_F81216H_CHIP_H
#define SUPERIO_FINTEK_F81216H_CHIP_H
#include <stdint.h>
/* Member variables are defined in devicetree.cb. */
struct superio_fintek_f81216h_config {
/**
* KEY1 KEY0 Enter key
* 0 0 0x77 (default)
* 0 1 0xA0
* 1 0 0x87
* 1 1 0x67
*
* See page 17 of data sheet.
*/
uint8_t conf_key_mode;
};
#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */

52
src/superio/fintek/f81216h/early_serial.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* This file is part of the coreboot project. */
#include <arch/io.h>
#include <device/pnp_ops.h>
#include <device/pnp.h>
#include <stdint.h>
#include "f81216h.h"
#define FINTEK_EXIT_KEY 0xAA
static void pnp_enter_conf_state(pnp_devfn_t dev, u8 f81216h_entry_key)
{
u16 port = dev >> 8;
outb(f81216h_entry_key, port);
outb(f81216h_entry_key, port);
}
static void pnp_exit_conf_state(pnp_devfn_t dev)
{
u16 port = dev >> 8;
outb(FINTEK_EXIT_KEY, port);
}
/* Bring up early serial debugging output before the RAM is initialized. */
void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, mode_key k)
{
u8 key;
switch (k) {
case MODE_6767:
key = 0x67;
break;
case MODE_7777:
key = 0x77;
break;
case MODE_8787:
key = 0x87;
break;
case MODE_A0A0:
key = 0xA0;
break;
default:
key = 0x77; /* try the hw default */
break;
}
pnp_enter_conf_state(dev, key);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}

31
src/superio/fintek/f81216h/f81216h.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* This file is part of the coreboot project. */
#ifndef SUPERIO_FINTEK_F81216H_H
#define SUPERIO_FINTEK_F81216H_H
#include <device/pnp_type.h>
/* Logical Device Numbers (LDN). */
#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */
#define F81216H_SP2 0x01 /* UART2 */
#define F81216H_SP3 0x02 /* UART3 */
#define F81216H_SP4 0x03 /* UART4 */
#define F81216H_WDT 0x08 /* WDT */
/**
* The PNP config entry key is parameterised
* by two bits on this Super I/O with 0x77 as
* the default key.
* See page 17 of data sheet for details.
*/
typedef enum {
MODE_6767 = 0x67,
MODE_7777 = 0x77,
MODE_8787 = 0x87,
MODE_A0A0 = 0xA0,
} mode_key;
void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, mode_key k);
#endif /* SUPERIO_FINTEK_F81216H_H */

98
src/superio/fintek/f81216h/superio.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/* This file is part of the coreboot project. */
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
#include <superio/conf_mode.h>
#include <console/console.h>
#include "chip.h"
#include "f81216h.h"
static void pnp_enter_ext_func_mode(struct device *dev)
{
const struct superio_fintek_f81216h_config *conf = dev->chip_info;
u8 key;
/**
* KEY1 KEY0 Enter key
* 0 0 0x77 (default)
* 0 1 0xA0
* 1 0 0x87
* 1 1 0x67
*
* See page 17 of data sheet.
*/
switch (conf->conf_key_mode) {
case MODE_6767:
case MODE_7777:
case MODE_8787:
case MODE_A0A0:
key = conf->conf_key_mode;
break;
default:
printk(BIOS_WARNING, "Warning: Undefined F81216 unlock key assignment!\n");
printk(BIOS_WARNING, "Setting conf_key_mode to default\n");
key = MODE_7777; /* try the hw default */
break;
}
outb(key, dev->path.pnp.port);
outb(key, dev->path.pnp.port);
}
static void pnp_exit_ext_func_mode(struct device *dev)
{
outb(0xaa, dev->path.pnp.port);
}
static const struct pnp_mode_ops pnp_conf_mode_ops = {
.enter_conf_mode = pnp_enter_ext_func_mode,
.exit_conf_mode = pnp_exit_ext_func_mode,
};
static void f81216h_init(struct device *dev)
{
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
case F81216H_SP1:
case F81216H_SP2:
case F81216H_SP3:
case F81216H_SP4:
case F81216H_WDT:
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_alt_enable,
.init = f81216h_init,
.ops_pnp_mode = &pnp_conf_mode_ops,
};
static struct pnp_info pnp_dev_info[] = {
{ NULL, F81216H_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, F81216H_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, F81216H_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, F81216H_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, F81216H_WDT, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_fintek_f81216h_ops = {
CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O")
.enable_dev = enable_dev
};