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intel/amenia: Update flash size to 16MB

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Update flash image size to 16MB and update image layout
in flashmap descriptor file.

BUG=chrome-os-partner:51844
TEST=Boot to chrome

Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/16083
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Bora Guvendik 2016-08-05 14:18:20 -07:00 committed by Martin Roth
parent c1645faeff
commit 2a31fcd6f8
2 changed files with 52 additions and 41 deletions
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7
src/mainboard/intel/amenia/Kconfig
View File

@ -3,8 +3,7 @@ if BOARD_INTEL_AMENIA
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select SOC_INTEL_APOLLOLAKE select SOC_INTEL_APOLLOLAKE
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_16384
select MAINBOARD_HAS_CHROMEOS
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_LPC
select EC_GOOGLE_CHROMEEC_PD select EC_GOOGLE_CHROMEEC_PD
@ -34,10 +33,6 @@ config FMAP_FILE
string string
default "amenia" default "amenia"
config PREBUILT_SPI_IMAGE
string
default "amenia.bin.orig.a0"
config MAX_CPUS config MAX_CPUS
int int
default 8 default 8

86
src/mainboard/intel/amenia/chromeos.fmd
View File

@ -1,36 +1,52 @@
FLASH 8M { FLASH 16M {
WP_RO 4M { WP_RO@0x0 0x800000 {
SI_ALL 2M { SI_DESC@0x0 0x1000
SI_DESC 4K IFWI@0x1000 0x1ff000
bootblock@509056 32K RO_SECTION@0x200000 0x600000 {
} RO_VPD@0x0 0x4000
RO_SECTION@2M 2M { FMAP@0x4000 0x800
FMAP 2K RO_FRID@0x4800 0x40
RO_FRID 0x40 RO_FRID_PAD@0x4840 0x7c0
RO_VPD @4K 16K COREBOOT(CBFS)@0x5000 0x17b000
COREBOOT(CBFS) GBB@0x180000 0x40000
SIGN_CSE@0x180000 64K RO_UNUSED_1@0x1c0000 0x400000
GBB # logical boot partition 2. Remove with updated CSE
} SIGN_CSE@0x5c0000 0x10000
} RO_UNUSED_2@0x5d0000 0x30000
MISC_RW { }
RW_MRC_CACHE 64K }
RW_ELOG 16K MISC_RW@0x800000 0x1a000 {
RW_SHARED 16K { RW_MRC_CACHE@0x0 0x10000
SHARED_DATA 8K RW_ELOG@0x10000 0x4000
VBLOCK_DEV 8K RW_SHARED@0x14000 0x4000 {
} SHARED_DATA@0x0 0x2000
RW_VPD 8K VBLOCK_DEV@0x2000 0x2000
} }
RW_SECTION_A 0xf0000 { RW_VPD@0x18000 0x2000
VBLOCK_A 64K }
FW_MAIN_A(CBFS) 768K RW_SECTION_A@0x81a000 0x28f800 {
RW_FWID_A 64 VBLOCK_A@0x0 0x10000
} FW_MAIN_A(CBFS)@0x10000 0x27f7c0
RW_SECTION_B 0xf0000 { RW_FWID_A@0x28f7c0 0x40
VBLOCK_B 64K }
FW_MAIN_B(CBFS) 768K RW_SECTION_B@0xaa9800 0x28f800 {
RW_FWID_B 64 VBLOCK_B@0x0 0x10000
} FW_MAIN_B(CBFS)@0x10000 0x27f7c0
DEVICE_EXTENSION@7M 1M RW_FWID_B@0x28f7c0 0x40
}
RW_NVRAM@0xd39000 0x6000
RW_LEGACY(CBFS)@0xd3f000 0x200000
BIOS_UNUSABLE@0xf3f000 0x40000
DEVICE_EXTENSION@0xf7f000 0x80000
# Currently, it is required that the BIOS region be a multiple of 8KiB.
# This is required so that the recovery mechanism can find SIGN_CSE
# region aligned to 4K at the center of BIOS region. Since the
# descriptor at the beginning uses 4K and BIOS starts at an offset of
# 4K, a hole of 4K is created towards the end of the flash to compensate
# for the size requirement of BIOS region.
# FIT tool thus creates descriptor with following regions:
# Descriptor --> 0 to 4K
# BIOS --> 4K to 0xf7f000
# Device ext --> 0xf7f000 to 0xfff000
UNUSED_HOLE@0xfff000 0x1000
} }