sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76: Enable SrcClk pin for CPU PCIe RPs

Browse Source 
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").

Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.

Set them now that RTD3 supports mapping the index for the CPU RP.

Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2022-01-07 14:12:34 -07:00 committed by Felix Held
parent b65c3015b0
commit 2a404b599b
6 changed files with 6 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/system76/darp7/devicetree.cb
View File

@ -113,8 +113,7 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD1_CLKREQ#
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end

3
src/mainboard/system76/galp5/devicetree.cb
View File

@ -113,8 +113,7 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD1_CLKREQ#
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end

3
src/mainboard/system76/gaze16/variants/3050/overridetree.cb
View File

@ -13,8 +13,7 @@ chip soc/intel/tigerlake
register "enable_off_delay_ms" = "4"
register "reset_delay_ms" = "10"
register "reset_off_delay_ms" = "4"
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # GFX_CLKREQ0#
register "srcclk_pin" = "0" # GFX_CLKREQ0#
device generic 0 on end
end
end

3
src/mainboard/system76/gaze16/variants/3060/overridetree.cb
View File

@ -13,8 +13,7 @@ chip soc/intel/tigerlake
register "enable_off_delay_ms" = "4"
register "reset_delay_ms" = "10"
register "reset_off_delay_ms" = "4"
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # PEG_CLKREQ#
register "srcclk_pin" = "9" # PEG_CLKREQ#
device generic 0 on end
end
end

3
src/mainboard/system76/lemp10/devicetree.cb
View File

@ -114,8 +114,7 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD2_CLKREQ#
register "srcclk_pin" = "3" # SSD2_CLKREQ#
device generic 0 on end
end
end

3
src/mainboard/system76/oryp8/devicetree.cb
View File

@ -99,8 +99,7 @@ chip soc/intel/tigerlake
register "enable_off_delay_ms" = "4"
register "reset_delay_ms" = "10"
register "reset_off_delay_ms" = "4"
# TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # PEG_CLKREQ#
register "srcclk_pin" = "9" # PEG_CLKREQ#
device generic 0 on end
end
end