nb/intel/sandybridge: Rename and refactor discover_timC_write
This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
committed by
Patrick Georgi
parent
9fbb1b096f
commit
2a7d752aaa
@@ -2438,7 +2438,7 @@ int aggressive_read_training(ramctr_timing *ctrl)
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return 0;
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}
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static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank)
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{
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wait_for_iosav(channel);
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@@ -2450,9 +2450,15 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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wait_for_iosav(channel);
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}
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int discover_timC_write(ramctr_timing *ctrl)
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static void set_write_vref(const int channel, const u8 wr_vref)
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{
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const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f };
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MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24), wr_vref << 24);
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udelay(2);
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}
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int aggressive_write_training(ramctr_timing *ctrl)
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{
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const u8 wr_vref_offsets[3] = { 0, 0x0f, 0x2f };
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int i, pat;
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int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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@@ -2471,21 +2477,17 @@ int discover_timC_write(ramctr_timing *ctrl)
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upper[channel][slotrank][lane] = MAX_TIMC;
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}
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/*
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* Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization.
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* FIXME: This must only be done on Ivy Bridge.
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*/
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MCHBAR32(MCMNTS_SPARE) = 1;
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/* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */
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const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu);
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if (enable_iosav_opt)
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MCHBAR32(MCMNTS_SPARE) = 1;
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printram("discover timC write:\n");
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for (i = 0; i < 3; i++)
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for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) {
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FOR_ALL_POPULATED_CHANNELS {
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/* FIXME: Setting the Write VREF must only be done on Ivy Bridge */
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MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel),
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~0x3f000000, rege3c_b24[i] << 24);
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udelay(2);
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set_write_vref(channel, wr_vref_offsets[i]);
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for (pat = 0; pat < NUM_PATTERNS; pat++) {
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FOR_ALL_POPULATED_RANKS {
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@@ -2505,9 +2507,8 @@ int discover_timC_write(ramctr_timing *ctrl)
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}
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program_timings(ctrl, channel);
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test_timC_write (ctrl, channel, slotrank);
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test_aggressive_write(ctrl, channel, slotrank);
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/* FIXME: Another IVB-only register! */
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raw_stats[timC] = MCHBAR32(
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IOSAV_BYTE_SERROR_C_ch(channel));
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}
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@@ -2546,18 +2547,16 @@ int discover_timC_write(ramctr_timing *ctrl)
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}
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}
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}
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FOR_ALL_CHANNELS {
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/* FIXME: Setting the Write VREF must only be done on Ivy Bridge */
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MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000);
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udelay(2);
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}
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/*
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* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization.
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* FIXME: This must only be done on Ivy Bridge.
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*/
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MCHBAR32(MCMNTS_SPARE) = 0;
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FOR_ALL_CHANNELS {
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/* Restore nominal write Vref after training */
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set_write_vref(channel, 0);
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}
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/* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization */
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if (enable_iosav_opt)
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MCHBAR32(MCMNTS_SPARE) = 0;
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printram("CPB\n");
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@@ -417,7 +417,7 @@ int write_training(ramctr_timing *ctrl);
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int command_training(ramctr_timing *ctrl);
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int read_mpr_training(ramctr_timing *ctrl);
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int aggressive_read_training(ramctr_timing *ctrl);
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int discover_timC_write(ramctr_timing *ctrl);
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int aggressive_write_training(ramctr_timing *ctrl);
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void normalize_training(ramctr_timing *ctrl);
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int channel_test(ramctr_timing *ctrl);
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void set_scrambling_seed(ramctr_timing *ctrl);
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@@ -706,7 +706,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_
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if (err)
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return err;
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err = discover_timC_write(ctrl);
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err = aggressive_write_training(ctrl);
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if (err)
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return err;
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