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soc/intel/cmn/acpi: Add support for PCR_BASE_ADDRESS above 4 GiB

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This change updates the Northbridge ASL to conditionally include a
QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS`
is above 4 GiB.

If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the
PCH reserved range, the existing handling of `SM01` remains unchanged
(as a DWordMemory resource).

TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB,
verified ASL output.

Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-06-18 13:16:44 +00:00
parent 6fc8bd9a7b
commit 2a84b83349
1 changed files with 14 additions and 3 deletions
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17
src/soc/intel/common/block/acpi/acpi/northbridge.asl
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@@ -166,7 +166,12 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x10000, 0x1ffff, 0x00000000,
0x10000,,, PM02)
#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \
#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB))
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
0x00000000, 0x000000000, 0x00000000, 0x00000000,
0x00000000,,, SM01)
#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \
(CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE))
/* SBREG BAR if outside of PCH reserved resource */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -202,13 +207,19 @@ Method (_CRS, 0, Serialized)
PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20)
PLEN = PMAX - PMIN + 1
#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \
#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB))
CreateQwordField (MCRS, SM01._MIN, SMIN)
CreateQwordField (MCRS, SM01._MAX, SMAX)
CreateQwordField (MCRS, SM01._LEN, SLEN)
SMIN = P2SB_BAR
SLEN = P2SB_SIZE
SMAX = SMIN + SLEN - 1
#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \
(CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE))
/* Fix up SBREG BAR memory region if outside PCH reserved resource */
CreateDwordField (MCRS, SM01._MIN, SMIN)
CreateDwordField (MCRS, SM01._MAX, SMAX)
CreateDwordField (MCRS, SM01._LEN, SLEN)
SMIN = P2SB_BAR
SLEN = P2SB_SIZE
SMAX = SMIN + SLEN - 1