soc/intel/cannonlake: Add common ACPI support for CNL
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Aaron Durbin
parent
6732b4fcdc
commit
2b074d90ae
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select COMMON_FADT
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select GENERIC_GPIO_LIB
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select HAVE_HARD_RESET
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@@ -30,7 +31,9 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_RAMSTAGE
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select SMP
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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@@ -26,6 +26,7 @@ romstage-y += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += gpio.c
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117
src/soc/intel/cannonlake/acpi.c
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117
src/soc/intel/cannonlake/acpi.c
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@@ -0,0 +1,117 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <cpu/cpu.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/acpi.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <wrdd.h>
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void soc_fill_fadt(acpi_fadt_t *fadt)
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{
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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const struct device *dev = PCH_DEV_LPC;
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const struct soc_intel_cannonlake_config *config = dev->chip_info;
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if (config->PmTimerDisabled != 0)
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return;
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fadt->pm_tmr_blk = pmbase + PM1_TMR;
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fadt->pm_tmr_len = 4;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.resv = 0;
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fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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}
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uint32_t soc_read_sci_irq_select(void)
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{
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uintptr_t pmc_bar = soc_read_pmc_base();
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return read32((void *)pmc_bar + IRQ_REG);
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}
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void acpi_create_gnvs(struct global_nvs_t *gnvs)
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{
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const struct device *dev = PCH_DEV_LPC;
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const struct soc_intel_cannonlake_config *config = dev->chip_info;
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/* Set unknown wake source */
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gnvs->pm1i = -1;
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/* CPU core count */
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gnvs->pcnt = dev_count_cpu();
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if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
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/* Update the mem console pointer. */
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gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
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if (IS_ENABLED(CONFIG_CHROMEOS)) {
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/* Initialize Verified Boot data */
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chromeos_init_vboot(&(gnvs->chromeos));
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
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gnvs->chromeos.vbt2 = google_ec_running_ro() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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} else
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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}
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/* Enable DPTF based on mainboard configuration */
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gnvs->dpte = config->dptf_enable;
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/* Fill in the Wifi Region id */
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gnvs->cid1 = wifi_regulatory_domain();
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/* Set USB2/USB3 wake enable bitmaps. */
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gnvs->u2we = config->usb2_wake_enable_bitmap;
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gnvs->u3we = config->usb3_wake_enable_bitmap;
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}
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uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
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const struct chipset_power_state *ps)
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{
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/*
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* WAK_STS bit is set when the system is in one of the sleep states
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* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
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* this bit, the PMC will transition the system to the ON state and
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* can only be set by hardware and can only be cleared by writing a one
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* to this bit position.
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*/
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generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
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return generic_pm1_en;
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}
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int soc_madt_sci_irq_polarity(int sci)
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{
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return MP_IRQ_POLARITY_HIGH;
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}
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57
src/soc/intel/cannonlake/acpi/globalnvs.asl
Normal file
57
src/soc/intel/cannonlake/acpi/globalnvs.asl
Normal file
@@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Global Variables */
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Name (\PICM, 0) // IOAPIC/8259
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/*
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* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PCNT, 8, // 0x03 - Processor Count
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PPCM, 8, // 0x04 - Max PPC State
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TLVL, 8, // 0x05 - Throttle Level Limit
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LIDS, 8, // 0x06 - LID State
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PWRS, 8, // 0x07 - AC Power State
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CBMC, 32, // 0x08 - 0x0b AC Power State
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PM1I, 64, // 0x0c - 0x13 PM1 wake status bit
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GPEI, 64, // 0x14 - 0x17 GPE wake status bit
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DPTE, 8, // 0x1c - Enable DPTF
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NHLA, 64, // 0x1d - 0x24 NHLT Address
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NHLL, 32, // 0x25 - 0x28 NHLT Length
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CID1, 16, // 0x29 - 0x2a Wifi Country Identifier
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U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap
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U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap
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UIOR, 8, // 0x2f - UART debug controller init on S3 resume
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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}
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@@ -24,6 +24,68 @@
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#include <soc/ramstage.h>
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#include <string.h>
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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static const char *soc_acpi_name(struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_IGD: return "GFX0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_USBOTG: return "XDCI";
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case PCH_DEVFN_THERMAL: return "THRM";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_CSE: return "CSE1";
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case PCH_DEVFN_CSE_2: return "CSE2";
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case PCH_DEVFN_CSE_IDER: return "CSED";
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case PCH_DEVFN_CSE_KT: return "CSKT";
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case PCH_DEVFN_CSE_3: return "CSE3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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case PCH_DEVFN_PCIE4: return "RP04";
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case PCH_DEVFN_PCIE5: return "RP05";
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case PCH_DEVFN_PCIE6: return "RP06";
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case PCH_DEVFN_PCIE7: return "RP07";
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case PCH_DEVFN_PCIE8: return "RP08";
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case PCH_DEVFN_PCIE9: return "RP09";
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_GSPI2: return "SPI2";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_LPC: return "LPCB";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_SPI: return "FSPI";
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case PCH_DEVFN_GBE: return "IGBE";
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case PCH_DEVFN_TRACEHUB:return "THUB";
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}
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return NULL;
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}
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#endif
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void soc_init_pre_device(void *chip_info)
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{
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/* Perform silicon specific init. */
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@@ -40,6 +102,9 @@ static struct device_operations pci_domain_ops = {
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_bus_default_ops,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.acpi_name = &soc_acpi_name,
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#endif
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};
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static struct device_operations cpu_bus_ops = {
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@@ -108,6 +108,11 @@ struct soc_intel_cannonlake_config {
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struct usb3_port_config usb3_ports[10];
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uint8_t XdciEnable;
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uint8_t SsicPortEnable;
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/* Wake Enable Bitmap for USB2 ports */
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* SATA related */
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uint8_t SataEnable;
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@@ -194,6 +199,7 @@ struct soc_intel_cannonlake_config {
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* 0x02000000 - 32MiB and beyond
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*/
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uint32_t PrmrrSize;
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uint8_t PmTimerDisabled;
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};
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typedef struct soc_intel_cannonlake_config config_t;
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@@ -248,4 +248,5 @@
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#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
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#define TOTAL_PADS 188
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#endif
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50
src/soc/intel/cannonlake/include/soc/nvs.h
Normal file
50
src/soc/intel/cannonlake/include/soc/nvs.h
Normal file
@@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_NVS_H_
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#define _SOC_NVS_H_
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#include <compiler.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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typedef struct global_nvs_t {
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/* Miscellaneous */
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u16 osys; /* 0x00 - 0x01 Operating System */
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u8 smif; /* 0x02 - SMI function call ("TRAP") */
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u8 pcnt; /* 0x03 - Processor Count */
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u8 ppcm; /* 0x04 - Max PPC State */
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u8 tlvl; /* 0x05 - Throttle Level Limit */
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u8 lids; /* 0x06 - LID State */
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u8 pwrs; /* 0x07 - AC Power State */
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u32 cbmc; /* 0x08 - 0xb AC Power State */
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u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
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u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
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u8 dpte; /* 0x1c - Enable DPTF */
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u64 nhla; /* 0x1d - 0x24 NHLT Address */
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u32 nhll; /* 0x25 - 0x28 NHLT Length */
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u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */
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u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
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u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
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u8 uior; /* 0x2f - UART debug controller init on S3 resume */
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u8 unused[208];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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#endif
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@@ -140,6 +140,11 @@
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#define ENABLE_SMI_PARAMS \
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(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
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#define PSS_RATIO_STEP 2
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#define PSS_MAX_ENTRIES 8
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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@@ -154,9 +159,6 @@ struct chipset_power_state {
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uint32_t prev_sleep_state;
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} __packed;
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/* Return the selected ACPI SCI IRQ */
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int acpi_sci_irq(void);
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/* Get base address PMC memory mapped registers. */
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uint8_t *pmc_mmio_regs(void);
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@@ -119,6 +119,8 @@
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#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
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#define GBLRST_CAUSE1 0x1928
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#define IRQ_REG ACTL
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#define SCI_IRQ_ADJUST 0
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#define ACTL 0x1BD8
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#define PWRM_EN (1 << 8)
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#define ACPI_EN (1 << 7)
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@@ -125,34 +125,6 @@ const char *const *soc_gpe_sts_array(size_t *a)
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return gpe_sts_bits;
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}
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int acpi_sci_irq(void)
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{
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int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
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int sci_irq = 9;
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/* Determine how SCI is routed. */
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switch (scis) {
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case SCIS_IRQ9:
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case SCIS_IRQ10:
|
||||
case SCIS_IRQ11:
|
||||
sci_irq = scis - SCIS_IRQ9 + 9;
|
||||
break;
|
||||
case SCIS_IRQ20:
|
||||
case SCIS_IRQ21:
|
||||
case SCIS_IRQ22:
|
||||
case SCIS_IRQ23:
|
||||
sci_irq = scis - SCIS_IRQ20 + 20;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
|
||||
sci_irq = 9;
|
||||
break;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
|
||||
return sci_irq;
|
||||
}
|
||||
|
||||
uint8_t *pmc_mmio_regs(void)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
Reference in New Issue
Block a user