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soc/intel/cannonlake: Add common ACPI support for CNL

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Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.

Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
2017-08-17 14:25:24 -07:00
committed by Aaron Durbin
parent 6732b4fcdc
commit 2b074d90ae
11 changed files with 307 additions and 31 deletions
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28
src/soc/intel/cannonlake/pmutil.c
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@@ -125,34 +125,6 @@ const char *const *soc_gpe_sts_array(size_t *a)
return gpe_sts_bits;
}
int acpi_sci_irq(void)
{
int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
int sci_irq = 9;
/* Determine how SCI is routed. */
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = scis - SCIS_IRQ9 + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = scis - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}
uint8_t *pmc_mmio_regs(void)
{
uint32_t reg32;