sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3

Browse Source 
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-02-28 20:10:20 +00:00
committed by Stefan Reinauer
parent 3c924d2f48
commit 2b34db8d1d
99 changed files with 433 additions and 345 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/southbridge/amd/amd8111/amd8111.c
View File

@@ -17,17 +17,17 @@ void amd8111_enable(device_t dev)
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
devfn = bus_dev->path.u.pci.devfn + (1 << 3);
devfn = bus_dev->path.pci.devfn + (1 << 3);
lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8;
if (dev->path.u.pci.devfn == 2) { /* EHCI */
index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
if (dev->path.pci.devfn == 2) { /* EHCI */
index = 16;
}
} else {
unsigned devfn;
devfn = (dev->path.u.pci.devfn) & ~7;
devfn = (dev->path.pci.devfn) & ~7;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
index = dev->path.u.pci.devfn & 7;
index = dev->path.pci.devfn & 7;
}
if ((!lpc_dev) || (index >= 17)) {
return;

8
src/southbridge/amd/amd8111/amd8111_acpi.c
View File

@@ -26,7 +26,7 @@ static int lsmbus_recv_byte(device_t dev)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_recv_byte(res->base, device);
@@ -37,7 +37,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_send_byte(res->base, device, val);
@@ -49,7 +49,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_read_byte(res->base, device, address);
@@ -60,7 +60,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_write_byte(res->base, device, address, val);

6
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@@ -46,8 +46,8 @@ static void amd8131_count_dev(device_t dev, void *ptr)
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
info->master_devices++;
}
if (PCI_FUNC(dev->path.u.pci.devfn) > info->max_func) {
info->max_func = PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
info->max_func = PCI_FUNC(dev->path.pci.devfn);
}
}
@@ -76,7 +76,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
if (sib == dev) {
continue;
}
if (PCI_SLOT(sib->path.u.pci.devfn) != PCI_SLOT(dev->path.u.pci.devfn)) {
if (PCI_SLOT(sib->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) {
continue;
}
sib_funcs++;

4
src/southbridge/amd/amd8132/amd8132_bridge.c
View File

@@ -83,8 +83,8 @@ static void amd8132_count_dev(device_t dev, void *ptr)
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
info->master_devices++;
}
if (PCI_FUNC(dev->path.u.pci.devfn) > info->max_func) {
info->max_func = PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
info->max_func = PCI_FUNC(dev->path.pci.devfn);
}
}

2
src/southbridge/amd/rs690/rs690.c
View File

@@ -144,7 +144,7 @@ void rs690_enable(device_t dev)
/* NOT REACHED */
}
dev_ind = dev->path.u.pci.devfn >> 3;
dev_ind = dev->path.pci.devfn >> 3;
switch (dev_ind) {
case 0: /* bus0, dev0, fun0; */
printk_info("Bus-0, Dev-0, Fun-0.\n");

8
src/southbridge/amd/rs690/rs690_cmn.c
View File

@@ -51,9 +51,9 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
dev->path.u.pci.devfn);
dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
dev->path.u.pci.devfn << 12 | reg;
dev->path.pci.devfn << 12 | reg;
return *((u32 *) addr);
}
@@ -64,9 +64,9 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
dev->path.u.pci.devfn);*/
dev->path.pci.devfn);*/
addr |= dev->bus->secondary << 20 | /* bus num */
dev->path.u.pci.devfn << 12 | reg_pos;
dev->path.pci.devfn << 12 | reg_pos;
reg = reg_old = *((u32 *) addr);
reg &= ~mask;

12
src/southbridge/amd/sb600/sb600.c
View File

@@ -146,13 +146,13 @@ void sb600_enable(device_t dev)
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) &&
(bus_dev->device == PCI_DEVICE_ID_ATI_SB600_PCI)) {
devfn = (bus_dev->path.u.pci.devfn) & ~7;
devfn = (bus_dev->path.pci.devfn) & ~7;
sm_dev = find_sm_dev(bus_dev, devfn);
if (!sm_dev)
return;
/* something under 00:01.0 */
switch (dev->path.u.pci.devfn) {
switch (dev->path.pci.devfn) {
case 5 << 3:
;
}
@@ -160,7 +160,7 @@ void sb600_enable(device_t dev)
return;
}
i = (dev->path.u.pci.devfn) & ~7;
i = (dev->path.pci.devfn) & ~7;
i += (2 << 3);
for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) {
sm_dev = find_sm_dev(dev, devfn);
@@ -170,7 +170,7 @@ void sb600_enable(device_t dev)
if (!sm_dev)
return;
switch (dev->path.u.pci.devfn - (devfn - (0x14 << 3))) {
switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
case (0x12 << 3) | 0:
index = 8;
set_sm_enable_bits(sm_dev, 0xac, 1 << index,
@@ -183,7 +183,7 @@ void sb600_enable(device_t dev)
case (0x13 << 3) | 3:
case (0x13 << 3) | 4:
case (0x13 << 3) | 5:
index = dev->path.u.pci.devfn & 7;
index = dev->path.pci.devfn & 7;
index++;
index %= 6;
set_sm_enable_bits(sm_dev, 0x68, 1 << index,
@@ -213,7 +213,7 @@ void sb600_enable(device_t dev)
break;
case (0x14 << 3) | 5:
case (0x14 << 3) | 6:
index = dev->path.u.pci.devfn & 7;
index = dev->path.pci.devfn & 7;
index -= 5;
set_pmio_enable_bits(sm_dev, 0x59, 1 << index,
(dev->enabled ? 0 : 1) << index);

8
src/southbridge/amd/sb600/sb600_sm.c
View File

@@ -302,7 +302,7 @@ static int lsmbus_recv_byte(device_t dev)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x10);
@@ -316,7 +316,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x10);
@@ -330,7 +330,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x10);
@@ -344,7 +344,7 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x10);

12
src/southbridge/broadcom/bcm5785/bcm5785.c
View File

@@ -21,21 +21,21 @@ void bcm5785_enable(device_t dev)
(bus_dev->device == 0x0036 )) // device under PCI-X Bridge
{
unsigned devfn;
devfn = bus_dev->path.u.pci.devfn + (1 << 3);
devfn = bus_dev->path.pci.devfn + (1 << 3);
sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
// index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8;
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
(bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
{
unsigned devfn;
devfn = bus_dev->bus->dev->path.u.pci.devfn + (1 << 3);
devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
// index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8;
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
}
else { // same bus
unsigned devfn;
uint32_t id;
devfn = (dev->path.u.pci.devfn) & ~7;
devfn = (dev->path.pci.devfn) & ~7;
if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if(dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
@@ -43,7 +43,7 @@ void bcm5785_enable(device_t dev)
{ devfn -= (1<<3); }
}
sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn);
// index = dev->path.u.pci.devfn & 7;
// index = dev->path.pci.devfn & 7;
}
if (!sb_pci_main_dev) {
return;

2
src/southbridge/broadcom/bcm5785/bcm5785_sata.c
View File

@@ -25,7 +25,7 @@ static void sata_init(struct device *dev)
volatile unsigned int *mmio_reg;
int i;
if(!(dev->path.u.pci.devfn & 7)) { // only set it in Func0
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
byte = pci_read_config8(dev, 0x78);
byte |= (1<<7);
pci_write_config8(dev, 0x78, byte);

8
src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
View File

@@ -71,7 +71,7 @@ static int lsmbus_recv_byte(device_t dev)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
@@ -85,7 +85,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
@@ -98,7 +98,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
@@ -111,7 +111,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);

8
src/southbridge/intel/esb6300/esb6300.c
View File

@@ -12,11 +12,11 @@ void esb6300_enable(device_t dev)
/* See if we are on the behind the 6300 pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
index = dev->path.u.pci.devfn & 7;
if((dev->path.pci.devfn &0xf8)== 0xf8) {
index = dev->path.pci.devfn & 7;
}
else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.u.pci.devfn & 7) +8;
else if((dev->path.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.pci.devfn & 7) +8;
}
if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
return;

2
src/southbridge/intel/esb6300/esb6300_smbus.c
View File

@@ -13,7 +13,7 @@ static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(bus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);

4
src/southbridge/intel/i3100/i3100.c
View File

@@ -41,8 +41,8 @@ void i3100_enable(device_t dev)
lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
disable = (volatile u32 *) 0xa0003418;
func = PCI_FUNC(dev->path.u.pci.devfn);
switch (PCI_SLOT(dev->path.u.pci.devfn)) {
func = PCI_FUNC(dev->path.pci.devfn);
switch (PCI_SLOT(dev->path.pci.devfn)) {
case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */
*disable |= (1 << (func == 0x0 ? 14 : func));
break;

2
src/southbridge/intel/i3100/i3100_smbus.c
View File

@@ -34,7 +34,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);

10
src/southbridge/intel/i82801ca/i82801ca.c
View File

@@ -22,16 +22,16 @@ void i82801ca_enable(device_t dev)
// D31:F1, D31:F3, D31:F5, D31:F6,
// D29:F0, D29:F1, D29:F2
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_SLOT(dev->path.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.pci.devfn);
if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
bHasDisableBit = 1;
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.pci.devfn);
if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
if (PCI_FUNC(dev->path.pci.devfn) < 3)
bHasDisableBit = 1;
}

10
src/southbridge/intel/i82801dbm/i82801dbm.c
View File

@@ -21,8 +21,8 @@ void i82801dbm_enable(device_t dev)
// D31: F0, F1, F3, F5, F6,
// D29: F0, F1, F2, F7
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_SLOT(dev->path.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.pci.devfn);
switch (index) {
case 0:
@@ -40,10 +40,10 @@ void i82801dbm_enable(device_t dev)
if (index == 0)
index = 14; // D31:F0 bit is an exception
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.pci.devfn);
if ((PCI_FUNC(dev->path.u.pci.devfn) < 3) || (PCI_FUNC(dev->path.u.pci.devfn) == 7))
if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7))
bHasDisableBit = 1;
}

8
src/southbridge/intel/i82801er/i82801er.c
View File

@@ -12,11 +12,11 @@ void i82801er_enable(device_t dev)
/* See if we are behind the i82801er pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
index = dev->path.u.pci.devfn & 7;
if((dev->path.pci.devfn &0xf8)== 0xf8) {
index = dev->path.pci.devfn & 7;
}
else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.u.pci.devfn & 7) +8;
else if((dev->path.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.pci.devfn & 7) +8;
}
if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
return;

2
src/southbridge/intel/i82801er/i82801er_smbus.c
View File

@@ -13,7 +13,7 @@ static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
unsigned device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(bus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);

2
src/southbridge/intel/i82801gx/i82801gx_smbus.c
View File

@@ -31,7 +31,7 @@ static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
u16 device;
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(bus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);

8
src/southbridge/intel/i82801xx/i82801xx.c
View File

@@ -40,10 +40,10 @@ void i82801xx_enable(device_t dev)
* exists it can be disabled. Workarounds for ICH variants that don't
* follow this should be done by checking the device ID.
*/
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn);
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
if (PCI_SLOT(dev->path.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.pci.devfn);
} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.pci.devfn);
}
/* Function 0 is a bit of an exception. */

2
src/southbridge/intel/i82801xx/i82801xx_smbus.c
View File

@@ -32,7 +32,7 @@ static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
unsigned device; /* TODO: u16? */
struct resource *res;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
res = find_resource(bus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);

4
src/southbridge/intel/i82870/p64h2_ioapic.c
View File

@@ -63,8 +63,8 @@ static void p64h2_ioapic_init(device_t dev)
pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
printk_debug("IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n",
apic_id, dev->bus->secondary, PCI_SLOT(dev->path.u.pci.devfn),
PCI_FUNC(dev->path.u.pci.devfn), pIndexRegister, pWindowRegister);
apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
apic_id <<= 24; // Convert ID to bitmask

4
src/southbridge/intel/pxhd/pxhd_bridge.c
View File

@@ -15,11 +15,11 @@ static void pxhd_enable(device_t dev)
{
device_t bridge;
uint16_t value;
if ((dev->path.u.pci.devfn & 1) == 0) {
if ((dev->path.pci.devfn & 1) == 0) {
/* Can we enable/disable the bridges? */
return;
}
bridge = dev_find_slot(dev->bus->secondary, dev->path.u.pci.devfn & ~1);
bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
if (!bridge) {
printk_err("Cannot find bridge for ioapic: %s\n",
dev_path(dev));

2
src/southbridge/nvidia/ck804/ck804.c
View File

@@ -61,7 +61,7 @@ void ck804_enable(device_t dev)
deviceid = dev->device;
}
devfn = (dev->path.u.pci.devfn) & ~7;
devfn = (dev->path.pci.devfn) & ~7;
switch (deviceid) {
case PCI_DEVICE_ID_NVIDIA_CK804_SM:
index = 16;

8
src/southbridge/nvidia/ck804/ck804_smbus.c
View File

@@ -20,7 +20,7 @@ static int lsmbus_recv_byte(device_t dev)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -34,7 +34,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -48,7 +48,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -62,7 +62,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));

4
src/southbridge/nvidia/mcp55/mcp55.c
View File

@@ -84,7 +84,7 @@ void mcp55_enable(device_t dev)
deviceid = dev->device;
}
devfn = (dev->path.u.pci.devfn) & ~7;
devfn = (dev->path.pci.devfn) & ~7;
switch(deviceid) {
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
return;
@@ -124,7 +124,7 @@ void mcp55_enable(device_t dev)
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
devfn -= (4<<3);
index = 22;
i = (dev->path.u.pci.devfn) & 7;
i = (dev->path.pci.devfn) & 7;
if(i>0) {
index -= (i+3);
}

8
src/southbridge/nvidia/mcp55/mcp55_smbus.c
View File

@@ -38,7 +38,7 @@ static int lsmbus_recv_byte(device_t dev)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -52,7 +52,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -66,7 +66,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
@@ -80,7 +80,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));

6
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@@ -54,7 +54,7 @@ static void rl5c476_init(device_t dev)
pci_write_config16(dev,0x82,0x00a0);
/* set up second slot as compact flash port if asked to do so */
if( enable_cf_boot && (PCI_FUNC(dev->path.u.pci.devfn) == 1)){
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
/* make sure isa interrupts are enabled */
pci_write_config16(dev,0x3e,0x0780);
@@ -154,7 +154,7 @@ void rl5c476_read_resources(device_t dev)
struct resource *resource;
/* for cf socket we need an extra memory window for the control structure of the cf itself */
if( enable_cf_boot && (PCI_FUNC(dev->path.u.pci.devfn) == 1)){
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = new_resource(dev,1); /* fake index as it isn't in pci config space */
resource->flags |= IORESOURCE_MEM ;
resource->size = 0x1000;
@@ -168,7 +168,7 @@ void rl5c476_set_resources(device_t dev)
{
struct resource *resource;
printk_debug("%s In set resources \n",dev_path(dev));
if( enable_cf_boot && (PCI_FUNC(dev->path.u.pci.devfn) == 1)){
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
if( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ;

2
src/southbridge/sis/sis966/sis761.c
View File

@@ -80,7 +80,7 @@ static void sis761_read_resources(device_t dev)
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) {
if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) {
printk_debug("sis761_not_the_first_processor !!!\n");
return;
}

4
src/southbridge/sis/sis966/sis966.c
View File

@@ -83,7 +83,7 @@ void sis966_enable(device_t dev)
deviceid = dev->device;
}
devfn = (dev->path.u.pci.devfn) & ~7;
devfn = (dev->path.pci.devfn) & ~7;
switch(deviceid) {
case PCI_DEVICE_ID_SIS_SIS966_USB:
devfn -= (1<<3);
@@ -115,7 +115,7 @@ void sis966_enable(device_t dev)
case PCI_DEVICE_ID_SIS_SIS966_SATA:
devfn -= (4<<3);
index = 22;
i = (dev->path.u.pci.devfn) & 7;
i = (dev->path.pci.devfn) & 7;
if(i>0) {
index -= (i+3);
}