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mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settings

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Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove
it to clean up a bit.

Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Felix Singer
2024-06-27 23:09:08 +02:00
parent 1f5a221a51
commit 2bca750f10
2 changed files with 0 additions and 5 deletions
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1
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@@ -181,7 +181,6 @@ chip soc/intel/tigerlake
device ref south_xhci on device ref south_xhci on
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), // Type-C Port1 [0] = USB2_PORT_MID(OC0), // Type-C Port1
[1] = USB2_PORT_EMPTY, // M.2 WWAN
[2] = USB2_PORT_MID(OC3), // M.2 Bluetooth [2] = USB2_PORT_MID(OC3), // M.2 Bluetooth
[3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1 [3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1
[4] = USB2_PORT_MID(OC0), // Type-C Port2 [4] = USB2_PORT_MID(OC0), // Type-C Port2

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -189,14 +189,10 @@ chip soc/intel/tigerlake
device ref south_xhci on device ref south_xhci on
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC3), // Type-C Port1 [0] = USB2_PORT_MID(OC3), // Type-C Port1
[1] = USB2_PORT_EMPTY, // M.2 WWAN
[2] = USB2_PORT_MID(OC0), // M.2 Bluetooth, USB3/2 Type A Port1 [2] = USB2_PORT_MID(OC0), // M.2 Bluetooth, USB3/2 Type A Port1
[3] = USB2_PORT_MID(OC3), // USB3/2 Type A Port 1 [3] = USB2_PORT_MID(OC3), // USB3/2 Type A Port 1
[4] = USB2_PORT_MID(OC3), // Type-C Port2 [4] = USB2_PORT_MID(OC3), // Type-C Port2
[5] = USB2_PORT_MID(OC3), // Type-C Port3 / MECC [5] = USB2_PORT_MID(OC3), // Type-C Port3 / MECC
[6] = USB2_PORT_EMPTY, // Not used
[7] = USB2_PORT_EMPTY, // Not used
[8] = USB2_PORT_EMPTY, // Not used
[9] = USB2_PORT_MID(OC3), // CNVi/BT [9] = USB2_PORT_MID(OC3), // CNVi/BT
}" }"