Initial AMD Serengeti_Cheetah_FAM10 platform for Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
parent
0da5cdeac2
commit
2ce8bfd251
424
src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
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424
src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
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@ -0,0 +1,424 @@
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#
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# This file is part of the LinuxBIOS project.
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#
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# Copyright (C) 2007 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FAILOVER_IMAGE
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
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else
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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#
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if USE_FAILOVER_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
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else
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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end
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end
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#needed by irq_tables and mptable and acpi_tables
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object get_bus_conf.o
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if HAVE_MP_TABLE
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object mptable.o
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end
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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if HAVE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
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action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
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action "mv dsdt_lb.hex dsdt.c"
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end
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object ./dsdt.o
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#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
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if ACPI_SSDTX_NUM
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makerule ssdt2.c
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depends "$(MAINBOARD)/dx/pci2.asl"
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action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
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action "mv pci2.hex ssdt2.c"
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end
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object ./ssdt2.o
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makerule ssdt3.c
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depends "$(MAINBOARD)/dx/pci3.asl"
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action "iasl -tc $(MAINBOARD)/dx/pci3.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
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action "mv pci3.hex ssdt3.c"
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end
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object ./ssdt3.o
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makerule ssdt4.c
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depends "$(MAINBOARD)/dx/pci4.asl"
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action "iasl -tc $(MAINBOARD)/dx/pci4.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
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action "mv pci4.hex ssdt4.c"
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end
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object ./ssdt4.o
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makerule ssdt5.c
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depends "$(MAINBOARD)/dx/pci5.asl"
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action "iasl -tc $(MAINBOARD)/dx/pci5.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
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action "mv pci5.hex ssdt5.c"
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end
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object ./ssdt5.o
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end
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end
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if USE_DCACHE_RAM
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makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
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if CONFIG_USE_INIT
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# compile cache_as_ram.c to auto.o
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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#compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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end
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_DCACHE_RAM
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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else
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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##
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## Include the secondary Configuration files
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##
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if CONFIG_CHIP_NAME
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config chip.h
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end
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dir /southbridge/amd/amd8151
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# sample config for amd/serengeti_cheetah_fam10
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chip northbridge/amd/amdfam10/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_F_1207 #L1 and DDR2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdfam10
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device pci 18.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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chip southbridge/amd/amd8132
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# the on/off keyword is mandatory
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 off end
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device pci 1.0 off end
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end
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device pci 1.0 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on
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chip drivers/i2c/i2cmux2 # pca9556 smbus mux
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chip drivers/i2c/i2cmux2 # pca9556 smbus mux
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device i2c 18 on #0 pca9516 1
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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end
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device i2c 18 on #1 pca9516 2
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chip drivers/generic/generic #dimm 1-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 1-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 1-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 1-1-1
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device i2c 53 on end
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end
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end
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end
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end
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end # acpi
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device pci 1.5 off end
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device pci 1.6 off end
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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end
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end # device pci 18.0
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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# device pci 00.5 on end
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end
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end #pci_domain
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#for node 32 to node 63
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# device pci_domain 0 on
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# chip northbridge/amd/amdfam10
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# device pci 00.0 on end# northbridge
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# device pci 00.0 on end
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# device pci 00.0 on end
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# device pci 00.0 on end
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||||
# device pci 00.1 on end
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||||
# device pci 00.2 on end
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||||
# device pci 00.3 on end
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||||
# device pci 00.4 on end
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# device pci 00.5 on end
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# end
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# end #pci_domain
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||||
|
||||
# chip drivers/generic/debug
|
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# device pnp 0.0 off end # chip name
|
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 off end # mem
|
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# device pnp 0.3 off end # cpuid
|
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
|
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# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
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# device pnp 0.8 off end # hard reset
|
||||
# device pnp 0.9 off end # mcp55
|
||||
# device pnp 0.a on end # GH ext table
|
||||
# end
|
||||
|
||||
end
|
||||
|
||||
|
||||
357
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
Normal file
357
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
Normal file
@ -0,0 +1,357 @@
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#
|
||||
# This file is part of the LinuxBIOS project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses HAVE_ACPI_TABLES
|
||||
uses ACPI_SSDTX_NUM
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_FAILOVER_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_FAILOVER_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses FAILOVER_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_ROM_PAYLOAD_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses OBJCOPY
|
||||
uses CONFIG_CHIP_NAME
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses HW_MEM_HOLE_SIZEK
|
||||
uses HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
|
||||
uses HT_CHAIN_UNITID_BASE
|
||||
uses HT_CHAIN_END_UNITID_BASE
|
||||
uses SB_HT_CHAIN_ON_BUS0
|
||||
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
uses DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses SERIAL_CPU_INIT
|
||||
|
||||
uses ENABLE_APIC_EXT_ID
|
||||
uses APIC_ID_OFFSET
|
||||
uses LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_LB_MEM_TOPK
|
||||
|
||||
uses PCI_BUS_SEGN_BITS
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses MEM_TRAIN_SEQ
|
||||
|
||||
uses WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_AMDMCT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CAR_FAM10
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
##
|
||||
#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
#default FALLBACK_SIZE=131072
|
||||
#default FALLBACK_SIZE=0x40000
|
||||
|
||||
#FALLBACK: 512K - 4K
|
||||
default FALLBACK_SIZE=0x7f000
|
||||
#FAILOVER: 4k
|
||||
default FAILOVER_SIZE=0x01000
|
||||
|
||||
#more 1M for pgtbl
|
||||
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
|
||||
default CONFIG_LB_MEM_TOPK=16384
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
default HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default HAVE_ACPI_TABLES=1
|
||||
## extra SSDT num
|
||||
default ACPI_SSDTX_NUM=31
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#default SERIAL_CPU_INIT=0
|
||||
|
||||
default ENABLE_APIC_EXT_ID=1
|
||||
default APIC_ID_OFFSET=0x00
|
||||
default LIFT_BSP_APIC_ID=1
|
||||
|
||||
#CHIP_NAME ?
|
||||
default CONFIG_CHIP_NAME=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one
|
||||
default HT_CHAIN_UNITID_BASE=0xa
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
default HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
#it only be 0, 1, 2, 3, 4 and default is 0
|
||||
#default PCI_BUS_SEGN_BITS=3
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default USE_DCACHE_RAM=1
|
||||
default DCACHE_RAM_BASE=0xc4000
|
||||
default DCACHE_RAM_SIZE=0x0c000
|
||||
#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
|
||||
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
#default CONFIG_AP_CODE_IN_CAR=1
|
||||
default MEM_TRAIN_SEQ=2
|
||||
default WAIT_BEFORE_CPUS_INIT=0
|
||||
|
||||
default CONFIG_AMDMCT = 1
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Cheetah Fam10"
|
||||
default MAINBOARD_VENDOR="AMD"
|
||||
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 768k heap
|
||||
##
|
||||
default HEAP_SIZE=0xc0000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00200000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
370
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
Normal file
370
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
Normal file
@ -0,0 +1,370 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
#define DUMP_ACPI_TABLES 0
|
||||
|
||||
#if DUMP_ACPI_TABLES == 1
|
||||
static void dump_mem(u32 start, u32 end)
|
||||
{
|
||||
|
||||
u32 i;
|
||||
print_debug("dump_mem:");
|
||||
for(i=start;i<end;i++) {
|
||||
if((i & 0xf)==0) {
|
||||
printk_debug("\n%08x:", i);
|
||||
}
|
||||
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
extern u8 AmlCode[];
|
||||
extern u8 AmlCode_ssdt[];
|
||||
|
||||
#if ACPI_SSDTX_NUM >= 1
|
||||
extern u8 AmlCode_ssdt2[];
|
||||
extern u8 AmlCode_ssdt3[];
|
||||
extern u8 AmlCode_ssdt4[];
|
||||
extern u8 AmlCode_ssdt5[];
|
||||
#endif
|
||||
|
||||
#define IO_APIC_ADDR 0xfec00000UL
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
/* Just a dummy */
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
u32 gsi_base=0x18;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write 8111 IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
/* Write all 8131 IOAPICs */
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
|
||||
res->base, gsi_base );
|
||||
gsi_base+=7;
|
||||
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
|
||||
res->base, gsi_base );
|
||||
gsi_base+=7;
|
||||
}
|
||||
}
|
||||
|
||||
int i;
|
||||
int j = 0;
|
||||
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
u32 d = 0;
|
||||
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
// 8131 need to use +4
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
d = 7;
|
||||
break;
|
||||
case 3:
|
||||
d = 4;
|
||||
break;
|
||||
}
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
|
||||
res->base, gsi_base );
|
||||
gsi_base+=d;
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
|
||||
res->base, gsi_base );
|
||||
gsi_base+=d;
|
||||
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 );
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edige-triggered, Active high*/
|
||||
|
||||
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapic_nmis(current, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
extern void update_ssdt(void *ssdt);
|
||||
|
||||
|
||||
void update_ssdtx(void *ssdtx, int i)
|
||||
{
|
||||
u8 *PCI;
|
||||
u8 *HCIN;
|
||||
u8 *UID;
|
||||
|
||||
PCI = ssdtx + 0x32;
|
||||
HCIN = ssdtx + 0x39;
|
||||
UID = ssdtx + 0x40;
|
||||
|
||||
if(i<7) {
|
||||
*PCI = (u8) ('4' + i - 1);
|
||||
}
|
||||
else {
|
||||
*PCI = (u8) ('A' + i - 1 - 6);
|
||||
}
|
||||
*HCIN = (u8) i;
|
||||
*UID = (u8) (i+3);
|
||||
|
||||
/* FIXME: need to update the GSI id in the ssdtx too */
|
||||
|
||||
}
|
||||
|
||||
unsigned long write_acpi_tables(unsigned long start)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_rsdp_t *rsdp;
|
||||
acpi_rsdt_t *rsdt;
|
||||
acpi_hpet_t *hpet;
|
||||
acpi_madt_t *madt;
|
||||
acpi_srat_t *srat;
|
||||
acpi_slit_t *slit;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_facs_t *facs;
|
||||
acpi_header_t *dsdt;
|
||||
acpi_header_t *ssdt;
|
||||
acpi_header_t *ssdtx;
|
||||
u8 *p;
|
||||
|
||||
int i;
|
||||
|
||||
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
|
||||
|
||||
/* Align ACPI tables to 16 bytes */
|
||||
start = ( start + 0x0f) & -0x10;
|
||||
current = start;
|
||||
|
||||
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * HPET at %lx\n", current);
|
||||
hpet = (acpi_hpet_t *) current;
|
||||
current += sizeof(acpi_hpet_t);
|
||||
acpi_create_hpet(hpet);
|
||||
acpi_add_table(rsdt,hpet);
|
||||
|
||||
/* If we want to use HPET Timers Linux wants an MADT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * MADT at %lx\n",current);
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current+=madt->header.length;
|
||||
acpi_add_table(rsdt,madt);
|
||||
|
||||
/* SRAT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * SRAT at %lx\n", current);
|
||||
srat = (acpi_srat_t *) current;
|
||||
acpi_create_srat(srat);
|
||||
current+=srat->header.length;
|
||||
acpi_add_table(rsdt,srat);
|
||||
|
||||
/* SLIT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * SLIT at %lx\n", current);
|
||||
slit = (acpi_slit_t *) current;
|
||||
acpi_create_slit(slit);
|
||||
current+=slit->header.length;
|
||||
acpi_add_table(rsdt,slit);
|
||||
|
||||
/* SSDT */
|
||||
current = ( current + 0x0f) & -0x10;
|
||||
printk_debug("ACPI: * SSDT at %lx\n", current);
|
||||
ssdt = (acpi_header_t *)current;
|
||||
current += ((acpi_header_t *)AmlCode_ssdt)->length;
|
||||
memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
|
||||
//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
|
||||
update_ssdt((void*)ssdt);
|
||||
/* recalculate checksum */
|
||||
ssdt->checksum = 0;
|
||||
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
|
||||
acpi_add_table(rsdt,ssdt);
|
||||
|
||||
printk_debug("ACPI: * SSDT for PState at %lx\n", current);
|
||||
current = acpi_add_ssdt_pstates(rsdt, current);
|
||||
|
||||
#if ACPI_SSDTX_NUM >= 1
|
||||
|
||||
/* same htio, but different possition? We may have to copy,
|
||||
change HCIN, and recalculate the checknum and add_table */
|
||||
|
||||
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
|
||||
if((sysconf.pci1234[i] & 1) != 1 ) continue;
|
||||
u8 c;
|
||||
if(i<7) {
|
||||
c = (u8) ('4' + i - 1);
|
||||
}
|
||||
else {
|
||||
c = (u8) ('A' + i - 1 - 6);
|
||||
}
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
|
||||
ssdtx = (acpi_header_t *)current;
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1:
|
||||
p = AmlCode_ssdt2;
|
||||
break;
|
||||
case 2:
|
||||
p = AmlCode_ssdt3;
|
||||
break;
|
||||
case 3: //8131
|
||||
p = AmlCode_ssdt4;
|
||||
break;
|
||||
default:
|
||||
//HTX no io apic
|
||||
p = AmlCode_ssdt5;
|
||||
}
|
||||
current += ((acpi_header_t *)p)->length;
|
||||
memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);
|
||||
update_ssdtx((void *)ssdtx, i);
|
||||
ssdtx->checksum = 0;
|
||||
ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
|
||||
acpi_add_table(rsdt,ssdtx);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DSDT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * DSDT at %lx\n", current);
|
||||
dsdt = (acpi_header_t *)current; // it will used by fadt
|
||||
current += ((acpi_header_t *)AmlCode)->length;
|
||||
memcpy((void *)dsdt,(void *)AmlCode, \
|
||||
((acpi_header_t *)AmlCode)->length);
|
||||
printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
|
||||
|
||||
/* FACS */ // it needs 64 bit alignment
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * FACS at %lx\n", current);
|
||||
facs = (acpi_facs_t *) current; // it will be used by fadt
|
||||
current += sizeof(acpi_facs_t);
|
||||
acpi_create_facs(facs);
|
||||
|
||||
/* FDAT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk_debug("ACPI: * FADT at %lx\n", current);
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
|
||||
acpi_create_fadt(fadt,facs,dsdt);
|
||||
acpi_add_table(rsdt,fadt);
|
||||
|
||||
#if DUMP_ACPI_TABLES == 1
|
||||
printk_debug("rsdp\n");
|
||||
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
|
||||
|
||||
printk_debug("rsdt\n");
|
||||
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
|
||||
|
||||
printk_debug("madt\n");
|
||||
dump_mem(madt, ((void *)madt) + madt->header.length);
|
||||
|
||||
printk_debug("srat\n");
|
||||
dump_mem(srat, ((void *)srat) + srat->header.length);
|
||||
|
||||
printk_debug("slit\n");
|
||||
dump_mem(slit, ((void *)slit) + slit->header.length);
|
||||
|
||||
printk_debug("ssdt\n");
|
||||
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
|
||||
|
||||
printk_debug("fadt\n");
|
||||
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
|
||||
#endif
|
||||
|
||||
printk_info("ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
||||
115
src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
Normal file
115
src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
|
||||
|
||||
#define SET_NB_CFG_54 1
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
#include "arch/i386/lib/console.c"
|
||||
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include "northbridge/amd/amdfam10/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
|
||||
#include "lib/delay.c"
|
||||
|
||||
#if NODE_NUMS == 64
|
||||
#define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn))
|
||||
#else
|
||||
#define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn)
|
||||
#endif
|
||||
|
||||
//#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdfam10/reset_test.c"
|
||||
#include "northbridge/amd/amdfam10/debug.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
|
||||
#include "cpu/x86/mtrr.h"
|
||||
#include "cpu/amd/mtrr.h"
|
||||
#include "cpu/x86/tsc.h"
|
||||
|
||||
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
|
||||
#include "northbridge/amd/amdfam10/amdfam10_conf.c"
|
||||
#include "northbridge/amd/amdfam10/raminit_ddr2_dqs.c"
|
||||
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
|
||||
void hardwaremain(int ret_addr)
|
||||
{
|
||||
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
|
||||
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
|
||||
|
||||
struct node_core_id id;
|
||||
|
||||
id = get_node_core_id_x();
|
||||
|
||||
printk_debug("CODE IN CACHE ON NODE: %02x\n");
|
||||
|
||||
train_ram(id.nodeid, sysinfo, sysinfox);
|
||||
|
||||
/* go back, but can not use stack any more, because we only keep
|
||||
ret_addr and can not restore esp, and ebp */
|
||||
|
||||
__asm__ volatile (
|
||||
"movl %0, %%edi\n\t"
|
||||
"jmp *%%edi\n\t"
|
||||
:: "a"(ret_addr)
|
||||
);
|
||||
|
||||
|
||||
|
||||
}
|
||||
struct eregs {
|
||||
u32 eax, ecx, edx, ebx, esp, ebp, esi, edi;
|
||||
u32 vector;
|
||||
u32 error_code;
|
||||
u32 eip;
|
||||
u32 cs;
|
||||
u32 eflags;
|
||||
};
|
||||
|
||||
void x86_exception(struct eregs *info)
|
||||
{
|
||||
do {
|
||||
hlt();
|
||||
} while(1);
|
||||
}
|
||||
|
||||
|
||||
412
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
Normal file
412
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
Normal file
@ -0,0 +1,412 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#define SYSTEM_TYPE 0 /* SERVER */
|
||||
//#define SYSTEM_TYPE 1 /* DESKTOP */
|
||||
//#define SYSTEM_TYPE 2 /* MOBILE */
|
||||
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
|
||||
|
||||
#define DEBUG_SMBUS 1
|
||||
|
||||
#define SET_NB_CFG_54 1
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
//used by incoherent_ht
|
||||
#define FAM10_SCAN_PCI_BUS 0
|
||||
#define FAM10_ALLOCATE_IO_RANGE 0
|
||||
|
||||
//used by init_cpus and fidvid
|
||||
#define FAM10_SET_FIDVID 1
|
||||
#define FAM10_SET_FIDVID_CORE_RANGE 0
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
/* FIXME: Use console.c post_code function */
|
||||
static void post_code(u8 value) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
|
||||
#if (USE_FAILOVER_IMAGE == 0)
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||
#include "northbridge/amd/amdfam10/raminit.h"
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
#endif
|
||||
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdfam10/reset_test.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
|
||||
#if (USE_FAILOVER_IMAGE == 0)
|
||||
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
|
||||
#include "northbridge/amd/amdfam10/debug.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
//GPIO on amd8111 to enable MEMRST ????
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
#define SMBUS_HUB 0x18
|
||||
int ret,i;
|
||||
u8 device = ctrl->spd_switch_addr;
|
||||
|
||||
printk_debug("switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
|
||||
|
||||
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
|
||||
i=2;
|
||||
do {
|
||||
ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
|
||||
} while ((ret!=0) && (i-->0));
|
||||
smbus_write_byte(SMBUS_HUB, 0x03, 0);
|
||||
}
|
||||
|
||||
|
||||
static inline int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
int result;
|
||||
result = smbus_read_byte(device, address);
|
||||
return result;
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
#include "northbridge/amd/amdht/ht_wrapper.c"
|
||||
|
||||
#include "include/cpu/x86/mem.h"
|
||||
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
|
||||
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
|
||||
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
|
||||
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
#include "cpu/amd/model_10xxx/init_cpus.c"
|
||||
#include "cpu/amd/model_10xxx/fidvid.c"
|
||||
|
||||
#endif /* (USE_FAILOVER_IMAGE == 0) */
|
||||
|
||||
|
||||
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdfam10/early_ht.c"
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
int last_boot_normal_flag = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_flag) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the rom access for 4M */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal_flag) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */
|
||||
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0.
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
#if USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if (USE_FAILOVER_IMAGE==0)
|
||||
#include "spd_addr.h"
|
||||
#include "cpu/amd/microcode/microcode.c"
|
||||
#include "cpu/amd/model_10xxx/update_microcode.c"
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
int needs_reset = 0;
|
||||
u32 bsp_apicid = 0;
|
||||
u32 val;
|
||||
msr_t msr;
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); //mmconf is inited in init_cpus
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
printk_debug("\n");
|
||||
|
||||
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
// Load MPB
|
||||
val = cpuid_eax(1);
|
||||
printk_debug("Family_Model: %08x \n", val);
|
||||
|
||||
/* FIXME: Need to make sure that APs are updated with the microcode and Errata */
|
||||
update_microcode(val);
|
||||
post_code(0x33);
|
||||
|
||||
/* FIXME: This errata code needs to move out of the mainboard but I am not sure where to yet.*/
|
||||
/* FIXME: Check CPU revision to apply correct erratas */
|
||||
/* Rev B errata */
|
||||
/* Errata #169 - supercedes errata #131 */
|
||||
msr = rdmsr(0xC001001F);
|
||||
msr.hi |= 1 << (32 - 32);
|
||||
wrmsr(0xC001101F, msr);
|
||||
|
||||
/* Errata #202 [DIS_PIGGY_BACK_SCRUB]=1 */
|
||||
msr = rdmsr(0xC0011022);
|
||||
msr.hi |= 1 << 24;
|
||||
wrmsr(0xC0010022, msr);
|
||||
|
||||
/* 298 : FIXME: Fixed in B3/C1 */
|
||||
/* msr = rdmsr(0xC0010015);
|
||||
msr.lo |= 1 << 3;
|
||||
wrmsr(0xC0010015, msr);
|
||||
|
||||
msr = rdmsr(0xC0011023);
|
||||
msr.lo |= 1 << 1;
|
||||
wrmsr(0xC0010023, msr);
|
||||
*/
|
||||
/* FIXME: Erratum #254 revB1 BU_CFG[21]=1 */
|
||||
|
||||
|
||||
printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
|
||||
setup_mb_resource_map();
|
||||
post_code(0x34);
|
||||
|
||||
// dump_pci_device(PCI_DEV(CBB, CDB, 0));
|
||||
|
||||
printk_debug("bsp_apicid = %02x \n", bsp_apicid);
|
||||
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
post_code(0x35);
|
||||
|
||||
// FIXME: Add needs_reset check to HT links.
|
||||
amd_ht_init(sysinfo);
|
||||
// print_pci_devices();
|
||||
// dump_pci_devices();
|
||||
|
||||
post_code(0x36);
|
||||
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// Core0 on each node is configured. Now setup any additional cores.
|
||||
printk_debug("start_other_cores()\n");
|
||||
start_other_cores();
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
#if FAM10_SET_FIDVID == 1
|
||||
msr = rdmsr(0xc0010071);
|
||||
printk_debug("Begin MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
|
||||
/* FIXME: The sb fid change may survive the warm reset and only
|
||||
need to be done once.*/
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
post_code(0x39);
|
||||
|
||||
if (warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
} else {
|
||||
needs_reset |= (init_fidvid_bsp(bsp_apicid, sysinfo->nodes) << 31);
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
set_p0(); // Speed up the BSP!
|
||||
|
||||
// show final fid and vid
|
||||
msr=rdmsr(0xc0010071);
|
||||
printk_debug("End MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
// Reset for HT and FIDVID changes?
|
||||
if (needs_reset) {
|
||||
print_info("\tht reset -\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
die("After soft_reset_x - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
//enable cf9 for hard reset
|
||||
print_debug("enable_cf9_x()\n");
|
||||
enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
post_code(0x3C);
|
||||
|
||||
//It's the time to set ctrl in sysinfo now;
|
||||
printk_debug("fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
post_code(0x3D);
|
||||
|
||||
|
||||
printk_debug("enable_smbus()\n");
|
||||
enable_smbus();
|
||||
post_code(0x3E);
|
||||
|
||||
|
||||
memreset_setup();
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
post_code(0x40);
|
||||
printk_debug("raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
post_code(0x41);
|
||||
|
||||
|
||||
/*
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
|
||||
*/
|
||||
|
||||
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
|
||||
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
|
||||
|
||||
|
||||
// die("After MCT init before CAR disabled.");
|
||||
|
||||
post_code(0x42);
|
||||
printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif /* USE_FAILOVER_IMAGE==0 */
|
||||
26
src/mainboard/amd/serengeti_cheetah_fam10/chip.h
Normal file
26
src/mainboard/amd/serengeti_cheetah_fam10/chip.h
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
extern struct chip_operations mainboard_amd_serengeti_cheetah_fam10_ops;
|
||||
|
||||
struct mainboard_amd_serengeti_cheetah_fam10_config {
|
||||
// int fixup_scsi;
|
||||
// int fixup_vga;
|
||||
};
|
||||
98
src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout
Normal file
98
src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout
Normal file
@ -0,0 +1,98 @@
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 quad_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
180
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111.asl
Normal file
180
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111.asl
Normal file
@ -0,0 +1,180 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
//AMD8111
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
|
||||
// Update the Device Number according to SBDN
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
|
||||
Store (0x00, ^DNCG)
|
||||
}
|
||||
If (LNot (PICF)) {Return (PICM)}
|
||||
Else {Return (APIC)}
|
||||
}
|
||||
|
||||
Device (SBC3)
|
||||
{
|
||||
// acpi smbus it should be 0x00040003 if 8131 present
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
|
||||
}
|
||||
OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
|
||||
Field (PIRQ, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
PIBA, 8,
|
||||
PIDC, 8
|
||||
}
|
||||
//
|
||||
// OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
|
||||
// Field (TS3_, DWordAcc, NoLock, Preserve)
|
||||
// {
|
||||
// PTS3, 16
|
||||
// }
|
||||
//
|
||||
}
|
||||
|
||||
Device (HPET)
|
||||
{
|
||||
Name (HPT, 0x00)
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (_UID, 0x00)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
Include ("amd8111_pic.asl")
|
||||
|
||||
Include ("amd8111_isa.asl")
|
||||
|
||||
Device (TP2P)
|
||||
{
|
||||
// 8111 P2P and it should 0x00030000 when 8131 present
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x08, 0x01 }) }
|
||||
}
|
||||
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x00000001)
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x0F, 0x01 }) }
|
||||
}
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
|
||||
})
|
||||
|
||||
Name (PICM, Package (0x0C)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
|
||||
})
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
192
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111_isa.asl
Normal file
192
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111_isa.asl
Normal file
@ -0,0 +1,192 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
//AMD8111 isa
|
||||
|
||||
Device (ISA)
|
||||
{
|
||||
// lpc 0x00040000
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
|
||||
}
|
||||
|
||||
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
|
||||
Field (PIRY, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z000, 2, // Parallel Port Range
|
||||
, 1,
|
||||
ECP, 1, // ECP Enable
|
||||
FDC1, 1, // Floppy Drive Controller 1
|
||||
FDC2, 1, // Floppy Drive Controller 2
|
||||
Offset (0x01),
|
||||
Z001, 3, // Serial Port A Range
|
||||
SAEN, 1, // Serial Post A Enabled
|
||||
Z002, 3, // Serial Port B Range
|
||||
SBEN, 1 // Serial Post B Enabled
|
||||
}
|
||||
|
||||
Device (PIC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0000"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
|
||||
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {2}
|
||||
})
|
||||
}
|
||||
|
||||
Device (DMA1)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0200"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
|
||||
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
|
||||
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
|
||||
DMA (Compatibility, NotBusMaster, Transfer16) {4}
|
||||
})
|
||||
}
|
||||
|
||||
Device (TMR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0100"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {0}
|
||||
})
|
||||
}
|
||||
|
||||
Device (RTC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0B00"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {8}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SPKR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0800"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
|
||||
})
|
||||
}
|
||||
|
||||
Device (COPR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C04"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
|
||||
IRQ (Edge, ActiveHigh, Exclusive) {13}
|
||||
})
|
||||
}
|
||||
|
||||
Device (SYSR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x00)
|
||||
Name (SYR1, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //report Thor NVRAM
|
||||
IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //report Thor NVRAM
|
||||
IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
|
||||
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
|
||||
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
|
||||
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
|
||||
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
|
||||
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
|
||||
IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
|
||||
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
|
||||
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
|
||||
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
|
||||
IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
|
||||
})
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (SYR1)
|
||||
}
|
||||
}
|
||||
|
||||
Device (MEM)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
|
||||
Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
|
||||
Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
|
||||
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
|
||||
Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
|
||||
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
|
||||
})
|
||||
// Read the Video Memory length
|
||||
CreateDWordField (BUF0, 0x14, CLEN)
|
||||
CreateDWordField (BUF0, 0x10, CBAS)
|
||||
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Store (Local0, CLEN)
|
||||
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2M)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (FLG0, 0x04, Local0)
|
||||
If (LEqual (Local0, 0x04)) { Return (0x0F) }
|
||||
Else { Return (0x00) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PS2K)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
}
|
||||
Include ("superio.asl")
|
||||
|
||||
}
|
||||
|
||||
376
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111_pic.asl
Normal file
376
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8111_pic.asl
Normal file
@ -0,0 +1,376 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
//AMD8111 pic LNKA B C D
|
||||
|
||||
Device (LNKA)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x01)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
|
||||
Else { Return (0x0B) } //Enabled
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
Store (Local1, Local2)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{ // Routing enable
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
Store (Local1, Local2)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x03)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
Store (Local1, Local2)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFA, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFA, 0x01, IRA1)
|
||||
CreateByteField (BUFA, 0x02, IRA2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRA1)
|
||||
Store (Local4, IRA2)
|
||||
}
|
||||
|
||||
Return (BUFA)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRA1)
|
||||
CreateByteField (Arg0, 0x02, IRA2)
|
||||
ShiftLeft (IRA2, 0x08, Local0)
|
||||
Or (Local0, IRA1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0F"))
|
||||
Name (_UID, 0x04)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
|
||||
If (LEqual (Local0, 0x00)) { Return (0x09) }
|
||||
Else { Return (0x0B) }
|
||||
}
|
||||
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
|
||||
})
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_DIS, 0, NotSerialized)
|
||||
{
|
||||
Store (0x01, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
Store (Local1, Local2)
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local1)
|
||||
}
|
||||
|
||||
ShiftLeft (Local3, Local1, Local3)
|
||||
Not (Local3, Local3)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUFB, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateByteField (BUFB, 0x01, IRB1)
|
||||
CreateByteField (BUFB, 0x02, IRB2)
|
||||
Store (0x00, Local3)
|
||||
Store (0x00, Local4)
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
If (LNot (LEqual (Local1, 0x00)))
|
||||
{
|
||||
If (LGreater (Local1, 0x07))
|
||||
{
|
||||
Subtract (Local1, 0x08, Local2)
|
||||
ShiftLeft (One, Local2, Local4)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (Local1, 0x00))
|
||||
{
|
||||
ShiftLeft (One, Local1, Local3)
|
||||
}
|
||||
}
|
||||
|
||||
Store (Local3, IRB1)
|
||||
Store (Local4, IRB2)
|
||||
}
|
||||
|
||||
Return (BUFB)
|
||||
}
|
||||
|
||||
Method (_SRS, 1, NotSerialized)
|
||||
{
|
||||
CreateByteField (Arg0, 0x01, IRB1)
|
||||
CreateByteField (Arg0, 0x02, IRB2)
|
||||
ShiftLeft (IRB2, 0x08, Local0)
|
||||
Or (Local0, IRB1, Local0)
|
||||
Store (0x00, Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
While (LGreater (Local0, 0x00))
|
||||
{
|
||||
Increment (Local1)
|
||||
ShiftRight (Local0, 0x01, Local0)
|
||||
}
|
||||
|
||||
And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
|
||||
ShiftLeft (Local1, 0x04, Local1)
|
||||
Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
126
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8131_2.asl
Normal file
126
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8131_2.asl
Normal file
@ -0,0 +1,126 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001B },
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones))
|
||||
{
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
Store (0x00, ^DNCG)
|
||||
}
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0022 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones))
|
||||
{
|
||||
Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x04))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
134
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8132.asl
Normal file
134
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8132.asl
Normal file
@ -0,0 +1,134 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x14)
|
||||
{
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
|
||||
|
||||
//Cypress Slot B - PIRQ CDAB
|
||||
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
|
||||
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
|
||||
|
||||
//Cypress Slot C - PIRQ DABC
|
||||
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
|
||||
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
|
||||
|
||||
//Cypress Slot D - PIRQ ABCD
|
||||
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
|
||||
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
|
||||
})
|
||||
Name (PICM, Package (0x14)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
|
||||
Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
191
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8132_2.asl
Normal file
191
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8132_2.asl
Normal file
@ -0,0 +1,191 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Device (PG0A)
|
||||
{
|
||||
// 8132 pcix bridge
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x10)
|
||||
{
|
||||
// Slot 1 - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
|
||||
// Slot 2 - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x0018 },
|
||||
// Slot 3 - PIRQ CDAB
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x001A },
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0019 },
|
||||
// Slot 4 - PIRQ DABC
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x001B },
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x0018 },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0019 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x001A },
|
||||
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
|
||||
// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
//
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x10))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
Device (PG0B)
|
||||
{
|
||||
// 8132 pcix bridge 2
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x22, 0x01 }) }
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x10)
|
||||
{
|
||||
// Slot A - PIRQ ABCD
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 },
|
||||
// Slot A - PIRQ BCDA
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0020 },// Slot 1
|
||||
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0021 },
|
||||
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x0022 },
|
||||
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x001F },
|
||||
// Slot A - PIRQ CDAB
|
||||
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x0021 },// Slot 1
|
||||
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x0022 },
|
||||
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x001F },
|
||||
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x0020 },
|
||||
// Slot A - PIRQ DABC
|
||||
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x0022 },// Slot 1
|
||||
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x001F },
|
||||
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x0020 },
|
||||
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x0021 },
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
|
||||
|
||||
// Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
|
||||
//
|
||||
// Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 1
|
||||
// Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
|
||||
// Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
|
||||
//
|
||||
})
|
||||
|
||||
Name (DNCG, Ones)
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^DNCG, Ones)) {
|
||||
Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
|
||||
Store (0x00, Local1)
|
||||
While (LLess (Local1, 0x10))
|
||||
{
|
||||
// Update the GSI according to HCIN
|
||||
Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
|
||||
Add(Local2, Local0, Local0)
|
||||
Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
|
||||
Increment (Local1)
|
||||
}
|
||||
|
||||
Store (0x00, ^DNCG)
|
||||
|
||||
}
|
||||
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
48
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8151.asl
Normal file
48
src/mainboard/amd/serengeti_cheetah_fam10/dx/amd8151.asl
Normal file
@ -0,0 +1,48 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
// AMD8151
|
||||
Device (AGPB)
|
||||
{
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00010000))
|
||||
}
|
||||
|
||||
Name (APIC, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
|
||||
})
|
||||
Name (PICM, Package (0x04)
|
||||
{
|
||||
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF)) { Return (PICM) }
|
||||
Else { Return (APIC) }
|
||||
}
|
||||
}
|
||||
|
||||
329
src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl
Normal file
329
src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl
Normal file
@ -0,0 +1,329 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
//AMD FAM10 util for BUSB and res range
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
|
||||
Name (OSTB, Ones)
|
||||
Method (OSTP, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (^OSTB, Ones))
|
||||
{
|
||||
Store (0x00, ^OSTB)
|
||||
}
|
||||
|
||||
Return (^OSTB)
|
||||
}
|
||||
|
||||
Method (SEQL, 2, Serialized)
|
||||
{
|
||||
Store (SizeOf (Arg0), Local0)
|
||||
Store (SizeOf (Arg1), Local1)
|
||||
If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
|
||||
|
||||
Name (BUF0, Buffer (Local0) {})
|
||||
Store (Arg0, BUF0)
|
||||
Name (BUF1, Buffer (Local0) {})
|
||||
Store (Arg1, BUF1)
|
||||
Store (Zero, Local2)
|
||||
While (LLess (Local2, Local0))
|
||||
{
|
||||
Store (DerefOf (Index (BUF0, Local2)), Local3)
|
||||
Store (DerefOf (Index (BUF1, Local2)), Local4)
|
||||
If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
|
||||
|
||||
Increment (Local2)
|
||||
}
|
||||
|
||||
Return (One)
|
||||
}
|
||||
|
||||
|
||||
Method (DADD, 2, NotSerialized)
|
||||
{
|
||||
Store( Arg1, Local0)
|
||||
Store( Arg0, Local1)
|
||||
Add( ShiftLeft(Local1,16), Local0, Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
|
||||
Method (GHCE, 1, NotSerialized) // check if the HC enabled
|
||||
{
|
||||
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
|
||||
if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
|
||||
Else { Return (0x00) }
|
||||
}
|
||||
|
||||
Method (GHCN, 1, NotSerialized) // get the node num for the HC
|
||||
{
|
||||
Store (0x00, Local0)
|
||||
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
|
||||
Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
|
||||
{
|
||||
Store (0x00, Local0)
|
||||
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
|
||||
Store (ShiftRight( And (Local1, 0x700), 0x08), Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
|
||||
{
|
||||
Store (0x00, Local0)
|
||||
Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
|
||||
Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
|
||||
Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
|
||||
Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
Method (GBUS, 2, NotSerialized)
|
||||
{
|
||||
Store (0x00, Local0)
|
||||
While (LLess (Local0, 0x20)) // 32 ht links
|
||||
{
|
||||
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
|
||||
If (LEqual (And (Local1, 0x03), 0x03))
|
||||
{
|
||||
If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02)))
|
||||
{
|
||||
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08))))
|
||||
{
|
||||
Return (ShiftRight (And (Local1, 0x000FF000), 0x0c))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
Return (0x00)
|
||||
}
|
||||
|
||||
Method (GWBN, 2, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x0000, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0000,,,)
|
||||
})
|
||||
CreateWordField (BUF0, 0x08, BMIN)
|
||||
CreateWordField (BUF0, 0x0A, BMAX)
|
||||
CreateWordField (BUF0, 0x0E, BLEN)
|
||||
Store (0x00, Local0)
|
||||
While (LLess (Local0, 0x20))
|
||||
{
|
||||
Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
|
||||
If (LEqual (And (Local1, 0x03), 0x03))
|
||||
{
|
||||
If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02)))
|
||||
{
|
||||
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08))))
|
||||
{
|
||||
Store (ShiftRight (And (Local1, 0x000FF000), 0x0c), BMIN)
|
||||
Store (ShiftRight (Local1, 0x14), BMAX)
|
||||
Subtract (BMAX, BMIN, BLEN)
|
||||
Increment (BLEN)
|
||||
Return (RTAG (BUF0))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
Return (RTAG (BUF0))
|
||||
}
|
||||
|
||||
Method (GMEM, 2, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x00000000, // Address Range Minimum
|
||||
0x00000000, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00000000,,,
|
||||
, AddressRangeMemory, TypeStatic)
|
||||
})
|
||||
CreateDWordField (BUF0, 0x0A, MMIN)
|
||||
CreateDWordField (BUF0, 0x0E, MMAX)
|
||||
CreateDWordField (BUF0, 0x16, MLEN)
|
||||
Store (0x00, Local0)
|
||||
Store (0x00, Local4)
|
||||
Store (0x00, Local3)
|
||||
While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit )
|
||||
{
|
||||
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
|
||||
Increment (Local0)
|
||||
Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
|
||||
If (LEqual (And (Local1, 0x03), 0x03))
|
||||
{
|
||||
If (LEqual (Arg0, And (Local2, 0x3f)))
|
||||
{
|
||||
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04))))
|
||||
{
|
||||
Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
|
||||
Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
|
||||
Or (MMAX, 0xFFFF, MMAX)
|
||||
Subtract (MMAX, MMIN, MLEN)
|
||||
|
||||
If (Local4)
|
||||
{
|
||||
Concatenate (RTAG (BUF0), Local3, Local5)
|
||||
Store (Local5, Local3)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
|
||||
{
|
||||
Store (\_SB.PCI0.TOM1, MMIN)
|
||||
Subtract (MMAX, MMIN, MLEN)
|
||||
Increment (MLEN)
|
||||
}
|
||||
|
||||
Store (RTAG (BUF0), Local3)
|
||||
}
|
||||
|
||||
Increment (Local4)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
If (LNot (Local4))
|
||||
{
|
||||
Store (BUF0, Local3)
|
||||
}
|
||||
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Method (GIOR, 2, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x00000000, // Address Range Minimum
|
||||
0x00000000, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00000000,,,
|
||||
, TypeStatic)
|
||||
})
|
||||
CreateDWordField (BUF0, 0x0A, PMIN)
|
||||
CreateDWordField (BUF0, 0x0E, PMAX)
|
||||
CreateDWordField (BUF0, 0x16, PLEN)
|
||||
Store (0x00, Local0)
|
||||
Store (0x00, Local4)
|
||||
Store (0x00, Local3)
|
||||
While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit)
|
||||
{
|
||||
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
|
||||
Increment (Local0)
|
||||
Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
|
||||
If (LEqual (And (Local1, 0x03), 0x03))
|
||||
{
|
||||
If (LEqual (Arg0, And (Local2, 0x3f)))
|
||||
{
|
||||
If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04))))
|
||||
{
|
||||
Store (And (Local1, 0x01FFF000), PMIN)
|
||||
Store (And (Local2, 0x01FFF000), PMAX)
|
||||
Or (PMAX, 0x0FFF, PMAX)
|
||||
Subtract (PMAX, PMIN, PLEN)
|
||||
Increment (PLEN)
|
||||
|
||||
If (Local4)
|
||||
{
|
||||
Concatenate (RTAG (BUF0), Local3, Local5)
|
||||
Store (Local5, Local3)
|
||||
}
|
||||
Else
|
||||
{
|
||||
If (LGreater (PMAX, PMIN))
|
||||
{
|
||||
If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
|
||||
{
|
||||
Store (0x0D00, PMIN)
|
||||
Subtract (PMAX, PMIN, PLEN)
|
||||
Increment (PLEN)
|
||||
}
|
||||
|
||||
Store (RTAG (BUF0), Local3)
|
||||
Increment (Local4)
|
||||
}
|
||||
|
||||
If (And (Local1, 0x10))
|
||||
{
|
||||
Store (0x03B0, PMIN)
|
||||
Store (0x03DF, PMAX)
|
||||
Store (0x30, PLEN)
|
||||
If (Local4)
|
||||
{
|
||||
Concatenate (RTAG (BUF0), Local3, Local5)
|
||||
Store (Local5, Local3)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (RTAG (BUF0), Local3)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Increment (Local4)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
If (LNot (Local4))
|
||||
{
|
||||
Store (RTAG (BUF0), Local3)
|
||||
}
|
||||
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Method (RTAG, 1, NotSerialized)
|
||||
{
|
||||
Store (Arg0, Local0)
|
||||
Store (SizeOf (Local0), Local1)
|
||||
Subtract (Local1, 0x02, Local1)
|
||||
Multiply (Local1, 0x08, Local1)
|
||||
CreateField (Local0, 0x00, Local1, RETB)
|
||||
Store (RETB, Local2)
|
||||
Return (Local2)
|
||||
}
|
||||
}
|
||||
242
src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl
Normal file
242
src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl
Normal file
@ -0,0 +1,242 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
||||
{
|
||||
|
||||
// Scope (_PR)
|
||||
// {
|
||||
// Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
|
||||
// Processor (CPU1, 0x01, 0x00000000, 0x00) {}
|
||||
// Processor (CPU2, 0x02, 0x00000000, 0x00) {}
|
||||
// Processor (CPU3, 0x03, 0x00000000, 0x00) {}
|
||||
// }
|
||||
|
||||
Method (FWSO, 0, NotSerialized) { }
|
||||
|
||||
Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
|
||||
Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
|
||||
Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
|
||||
|
||||
Scope (_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
// BUS0 root bus
|
||||
External (BUSN)
|
||||
External (MMIO)
|
||||
External (PCIO)
|
||||
External (SBLK)
|
||||
External (TOM1)
|
||||
External (HCLK)
|
||||
External (SBDN)
|
||||
External (HCDN)
|
||||
External (CBST)
|
||||
External (CBB)
|
||||
External (CBS2)
|
||||
External (CBB2)
|
||||
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x01)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
|
||||
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
|
||||
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x8100, // Address Range Minimum
|
||||
0xFFFF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x7F00,,,
|
||||
, TypeStatic) //8100h-FFFFh
|
||||
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x000C0000, // Address Range Minimum
|
||||
0x00000000, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00000000,,,
|
||||
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
|
||||
|
||||
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x03AF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x03B0,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x03E0, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0918,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
})
|
||||
\_SB.OSTP ()
|
||||
CreateDWordField (BUF0, 0x3E, VLEN)
|
||||
CreateDWordField (BUF0, 0x36, VMAX)
|
||||
CreateDWordField (BUF0, 0x32, VMIN)
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Add (VMIN, Local0, VMAX)
|
||||
Decrement (VMAX)
|
||||
Store (Local0, VLEN)
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Include ("pci0_hc.asl")
|
||||
|
||||
}
|
||||
Device (PCI1)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBST)
|
||||
}
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBB) // 0 or 0xff
|
||||
}
|
||||
|
||||
}
|
||||
Device (PCI2)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBS2)
|
||||
}
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBB2)// 0xfe
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (_GPE)
|
||||
{
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
|
||||
}
|
||||
|
||||
Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0B, 0x02)
|
||||
}
|
||||
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
//
|
||||
// Method (_WAK, 1, NotSerialized)
|
||||
// {
|
||||
// Or (Arg0, 0xE0, Local0)
|
||||
// Store (Local0, DBG1)
|
||||
// }
|
||||
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
|
||||
Include ("amdfam10_util.asl")
|
||||
}
|
||||
@ -0,0 +1,35 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Device (HTXA)
|
||||
{
|
||||
// HTX
|
||||
Method (_ADR, 0, NotSerialized)
|
||||
{
|
||||
Return (DADD(GHCD(HCIN, 0), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_PRW, 0, NotSerialized)
|
||||
{
|
||||
If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
|
||||
Else { Return (Package (0x02) { 0x29, 0x01 }) }
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci0_hc.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci0_hc.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
Include ("amd8111.asl") //real SB at first
|
||||
Include ("amd8132.asl")
|
||||
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci2.asl
Normal file
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci2.asl
Normal file
@ -0,0 +1,83 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Include ("pci2_hc.asl")
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci2_hc.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci2_hc.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Include ("amd8132_2.asl")
|
||||
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci3.asl
Normal file
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci3.asl
Normal file
@ -0,0 +1,83 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Include ("pci3_hc.asl")
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci3_hc.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci3_hc.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Include ("amd8151.asl")
|
||||
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci4.asl
Normal file
83
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci4.asl
Normal file
@ -0,0 +1,83 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Include ("pci4_hc.asl")
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci4_hc.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci4_hc.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Include ("amd8131_2.asl")
|
||||
84
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci5.asl
Normal file
84
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci5.asl
Normal file
@ -0,0 +1,84 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
External (DADD, MethodObj)
|
||||
External (GHCE, MethodObj)
|
||||
External (GHCN, MethodObj)
|
||||
External (GHCL, MethodObj)
|
||||
External (GHCD, MethodObj)
|
||||
External (GNUS, MethodObj)
|
||||
External (GIOR, MethodObj)
|
||||
External (GMEM, MethodObj)
|
||||
External (GWBN, MethodObj)
|
||||
External (GBUS, MethodObj)
|
||||
|
||||
External (PICF)
|
||||
|
||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
||||
|
||||
Device (PCIX)
|
||||
{
|
||||
|
||||
// BUS ? Second HT Chain
|
||||
Name (HCIN, 0xcc) // HC2 0x01
|
||||
|
||||
Name (_UID, 0xdd) // HC 0x03
|
||||
|
||||
Name (_HID, "PNP0A03")
|
||||
|
||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
||||
{
|
||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
||||
}
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.GHCE(HCIN))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () { })
|
||||
Store( GHCN(HCIN), Local4)
|
||||
Store( GHCL(HCIN), Local5)
|
||||
|
||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
Include ("pci5_hc.asl")
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci5_hc.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/pci5_hc.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
Include ("htx_no_ioapic.asl")
|
||||
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/superio.asl
Normal file
20
src/mainboard/amd/serengeti_cheetah_fam10/dx/superio.asl
Normal file
@ -0,0 +1,20 @@
|
||||
//
|
||||
// This file is part of the LinuxBIOS project.
|
||||
//
|
||||
// Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; version 2 of the License.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
//
|
||||
|
||||
// Include ("w83627hf.asl")
|
||||
172
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
Normal file
172
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
Normal file
@ -0,0 +1,172 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2005 Stefan Reinauer <stepan@openbios.org>
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
extern u32 pm_base; /* pm_base should be set in sb acpi */
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
||||
|
||||
acpi_header_t *header=&(fadt->header);
|
||||
|
||||
printk_debug("pm_base: 0x%04x\n", pm_base);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt,0,sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature,"FACP",4);
|
||||
header->length = 244;
|
||||
header->revision = 1;
|
||||
memcpy(header->oem_id,OEM_ID,6);
|
||||
memcpy(header->oem_table_id,"LXBACPI ",8);
|
||||
memcpy(header->asl_compiler_id,ASLC,4);
|
||||
header->asl_compiler_revision=0;
|
||||
|
||||
fadt->firmware_ctrl=(u32)facs;
|
||||
fadt->dsdt= (u32)dsdt;
|
||||
fadt->res1=0x0;
|
||||
// 3=Workstation,4=Enterprise Server, 7=Performance Server
|
||||
fadt->preferred_pm_profile=0x03;
|
||||
fadt->sci_int=9;
|
||||
// disable system management mode by setting to 0:
|
||||
fadt->smi_cmd = 0;//pm_base+0x2f;
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0x00; // SMM is not used for p-state control
|
||||
// fadt->pstate_cnt = 0xe2;
|
||||
|
||||
fadt->pm1a_evt_blk = pm_base;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = pm_base+0x04;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = 0x0000;
|
||||
fadt->pm_tmr_blk = pm_base+0x08;
|
||||
fadt->gpe0_blk = pm_base+0x20;
|
||||
fadt->gpe1_blk = pm_base+0xb0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 0;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 4;
|
||||
fadt->gpe1_blk_len = 8;
|
||||
fadt->gpe1_base = 16;
|
||||
|
||||
fadt->cst_cnt = 0x00;// SMM is not used for p-state control
|
||||
// fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; // 0x7d these have to be
|
||||
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
|
||||
fadt->century = 0; // 0x7f to make rtc alrm work
|
||||
fadt->iapc_boot_arch = 0x3; // See table 5-11
|
||||
fadt->flags = 0x25;
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pm_base;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = pm_base+0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 64;
|
||||
fadt->x_gpe1_blk.bit_offset = 16;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = pm_base+0xb0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
|
||||
}
|
||||
229
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
Normal file
229
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
Normal file
@ -0,0 +1,229 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
|
||||
struct mb_sysconf_t mb_sysconf;
|
||||
|
||||
/* Here you only need to set value in pci1234 for HT-IO that could be
|
||||
installed or not You may need to preset pci1234 for HTIO board, please
|
||||
refer to src/northbridge/amd/amdfam10/get_sblk_pci1234.c for detail */
|
||||
static u32 pci1234x[] = {
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
|
||||
0x0000ffc, 0x0000ffc,
|
||||
};
|
||||
|
||||
|
||||
/* HT Chain device num, actually it is unit id base of every ht device
|
||||
in chain, assume every chain only have 4 ht device at most */
|
||||
|
||||
static unsigned hcdnx[] = {
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
|
||||
0x20202020, 0x20202020,
|
||||
};
|
||||
|
||||
|
||||
|
||||
extern void get_pci1234(void);
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
static u32 get_hcid(u32 i)
|
||||
{
|
||||
u32 id = 0;
|
||||
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
u32 devn = sysconf.hcdn[i] & 0xff;
|
||||
device_t dev;
|
||||
|
||||
dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
|
||||
|
||||
switch (dev->device) {
|
||||
case 0x7458: //8132
|
||||
id = 1;
|
||||
break;
|
||||
case 0x7454: //8151
|
||||
id = 2;
|
||||
break;
|
||||
case 0x7450: //8131
|
||||
id = 3;
|
||||
break;
|
||||
}
|
||||
// we may need more way to find out hcid: subsystem id? GPIO read ?
|
||||
// we need use id for 1. bus num, 2. mptable, 3. acpi table
|
||||
return id;
|
||||
}
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
|
||||
device_t dev;
|
||||
int i, j;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
if(get_bus_conf_done == 1)
|
||||
return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.mb = &mb_sysconf;
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
for(i=0;i<256; i++) {
|
||||
m->bus_type[i] = 0;
|
||||
}
|
||||
|
||||
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
|
||||
for(i=0;i<sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_pci1234();
|
||||
|
||||
m->bus_type[0] = 1; //pci
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
|
||||
m->sbdn3 = sysconf.hcdn[0] & 0xff;
|
||||
|
||||
m->bus_8132_0 = (sysconf.pci1234[0] >> 12) & 0xff;
|
||||
m->bus_8111_0 = m->bus_8132_0;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
|
||||
if (dev) {
|
||||
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
|
||||
}
|
||||
|
||||
/* 8132-1 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0));
|
||||
if (dev) {
|
||||
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
|
||||
if (dev) {
|
||||
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
|
||||
}
|
||||
|
||||
for(i=0; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
|
||||
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
u32 busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
|
||||
for (j = busn; j <= busn_max; j++)
|
||||
m->bus_type[j] = 1;
|
||||
if(m->bus_isa <= busn_max)
|
||||
m->bus_isa = busn_max + 1;
|
||||
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
|
||||
}
|
||||
|
||||
/* HT chain 1 */
|
||||
j=0;
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
|
||||
// check hcid type here
|
||||
sysconf.hcid[i] = get_hcid(i);
|
||||
|
||||
switch(sysconf.hcid[i]) {
|
||||
|
||||
case 1: //8132
|
||||
case 3: //8131
|
||||
|
||||
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
|
||||
m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
/* 8132-1 */
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
|
||||
if (dev) {
|
||||
m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case 2: //8151
|
||||
|
||||
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
|
||||
/* 8151 */
|
||||
dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
|
||||
|
||||
if (dev) {
|
||||
m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
apicid_base = 0;
|
||||
m->apicid_8111 = apicid_base + 0;
|
||||
m->apicid_8132_1 = apicid_base + 1;
|
||||
m->apicid_8132_2 = apicid_base + 2;
|
||||
for(i=0;i<j;i++) {
|
||||
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
|
||||
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
|
||||
}
|
||||
}
|
||||
144
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
Normal file
144
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
Normal file
@ -0,0 +1,144 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0,
|
||||
u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum=0;
|
||||
int i;
|
||||
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = m->bus_8111_0;
|
||||
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1022;
|
||||
pirq->rtr_device = 0x746b;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
|
||||
//pcix bridge
|
||||
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
// pirq_info++; slot_num++;
|
||||
|
||||
int j=0;
|
||||
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
|
||||
u32 devn = sysconf.hcdn[i] & 0xff;
|
||||
|
||||
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
j++;
|
||||
|
||||
}
|
||||
|
||||
#if CBB
|
||||
write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
if(sysconf.nodes>32) {
|
||||
write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++) {
|
||||
sum += v[i];
|
||||
}
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
|
||||
}
|
||||
32
src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
Normal file
32
src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if CONFIG_CHIP_NAME == 1
|
||||
struct chip_operations mainboard_amd_serengeti_cheetah_fam10_ops = {
|
||||
CHIP_NAME("AMD family 10 Cheetah mainboard")
|
||||
};
|
||||
#endif
|
||||
45
src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h
Normal file
45
src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MB_SYSCONF_H
|
||||
|
||||
#define MB_SYSCONF_H
|
||||
|
||||
struct mb_sysconf_t {
|
||||
u8 bus_isa;
|
||||
u8 bus_8132_0;
|
||||
u8 bus_8132_1;
|
||||
u8 bus_8132_2;
|
||||
u8 bus_8111_0;
|
||||
u8 bus_8111_1;
|
||||
u8 bus_8132a[31][3];
|
||||
u8 bus_8151[31][2];
|
||||
|
||||
u32 apicid_8111;
|
||||
u32 apicid_8132_1;
|
||||
u32 apicid_8132_2;
|
||||
u32 apicid_8132a[31][2];
|
||||
u32 sbdn3;
|
||||
u32 sbdn3a[31];
|
||||
u32 sbdn5[31];
|
||||
u32 bus_type[256];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
237
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
Normal file
237
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
Normal file
@ -0,0 +1,237 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "AMD ";
|
||||
static const char productid[12] = "SERENGETI ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
int i;
|
||||
int j;
|
||||
struct mb_sysconf_t *m;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
m = sysconf.mb;
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(j= 0; j < 256 ; j++) {
|
||||
if(m->bus_type[j])
|
||||
smp_write_bus(mc, j, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, m->bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
|
||||
j = 0;
|
||||
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
|
||||
//??? What
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
|
||||
|
||||
// Onboard AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
|
||||
|
||||
//Slot 3 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
|
||||
}
|
||||
|
||||
|
||||
// Slot 4 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
|
||||
}
|
||||
|
||||
|
||||
// Slot 1 PCI-X 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
|
||||
}
|
||||
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
|
||||
}
|
||||
|
||||
j = 0;
|
||||
|
||||
for(i=1; i< sysconf.hc_possible_num; i++) {
|
||||
if(!(sysconf.pci1234[i] & 0x1) ) continue;
|
||||
int ii;
|
||||
int jj;
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
switch(sysconf.hcid[i]) {
|
||||
case 1:
|
||||
case 3:
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
for(jj=0; jj<4; jj++) {
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
for(ii=0;ii<4;ii++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
for(jj=0; jj<4; jj++) {
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
for(ii=0;ii<4;ii++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case 2:
|
||||
|
||||
// Slot AGP
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
|
||||
break;
|
||||
}
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
281
src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
Normal file
281
src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
Normal file
@ -0,0 +1,281 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
|
||||
static void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10
|
||||
PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10
|
||||
PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
|
||||
PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
||||
194
src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h
Normal file
194
src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h
Normal file
@ -0,0 +1,194 @@
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file defines the SPD addresses for the mainboard. Must be included in
|
||||
* cache_as_ram_auto.c
|
||||
*/
|
||||
|
||||
#define RC00 0
|
||||
#define RC01 1
|
||||
#define RC02 2
|
||||
#define RC03 3
|
||||
#define RC04 4
|
||||
#define RC05 5
|
||||
#define RC06 6
|
||||
#define RC07 7
|
||||
#define RC08 8
|
||||
#define RC09 9
|
||||
#define RC10 10
|
||||
#define RC11 11
|
||||
#define RC12 12
|
||||
#define RC13 13
|
||||
#define RC14 14
|
||||
#define RC15 15
|
||||
#define RC16 16
|
||||
#define RC17 17
|
||||
#define RC18 18
|
||||
#define RC19 19
|
||||
#define RC20 20
|
||||
#define RC21 21
|
||||
#define RC22 22
|
||||
#define RC23 23
|
||||
#define RC24 24
|
||||
#define RC25 25
|
||||
#define RC26 26
|
||||
#define RC27 27
|
||||
#define RC28 28
|
||||
#define RC29 29
|
||||
#define RC30 30
|
||||
#define RC31 31
|
||||
|
||||
#define RC32 32
|
||||
#define RC33 33
|
||||
#define RC34 34
|
||||
#define RC35 35
|
||||
#define RC36 36
|
||||
#define RC37 37
|
||||
#define RC38 38
|
||||
#define RC39 39
|
||||
#define RC40 40
|
||||
#define RC41 41
|
||||
#define RC42 42
|
||||
#define RC43 43
|
||||
#define RC44 44
|
||||
#define RC45 45
|
||||
#define RC46 46
|
||||
#define RC47 47
|
||||
#define RC48 48
|
||||
#define RC49 49
|
||||
#define RC50 50
|
||||
#define RC51 51
|
||||
#define RC52 52
|
||||
#define RC53 53
|
||||
#define RC54 54
|
||||
#define RC55 55
|
||||
#define RC56 56
|
||||
#define RC57 57
|
||||
#define RC58 58
|
||||
#define RC59 59
|
||||
#define RC60 60
|
||||
#define RC61 61
|
||||
#define RC62 62
|
||||
#define RC63 63
|
||||
|
||||
|
||||
#define DIMM0 0x50
|
||||
#define DIMM1 0x51
|
||||
#define DIMM2 0x52
|
||||
#define DIMM3 0x53
|
||||
#define DIMM4 0x54
|
||||
#define DIMM5 0x55
|
||||
#define DIMM6 0x56
|
||||
#define DIMM7 0x57
|
||||
|
||||
|
||||
static const u8 spd_addr[] = {
|
||||
//first node
|
||||
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
//second node
|
||||
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 2
|
||||
// third node
|
||||
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
// forth node
|
||||
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 4
|
||||
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 6
|
||||
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 8
|
||||
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 12
|
||||
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 16
|
||||
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 20
|
||||
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 24
|
||||
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 32
|
||||
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 48
|
||||
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
67
targets/amd/serengeti_cheetah_fam10/Config.lb
Normal file
67
targets/amd/serengeti_cheetah_fam10/Config.lb
Normal file
@ -0,0 +1,67 @@
|
||||
##
|
||||
## This file is part of the LinuxBIOS project.
|
||||
##
|
||||
## Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# Sample config file for
|
||||
# the amd cheetah_fam10
|
||||
# This will make a target directory of ./serengeti_cheetah_fam10
|
||||
|
||||
target serengeti_cheetah_fam10
|
||||
mainboard amd/serengeti_cheetah_fam10
|
||||
# Request this level of debugging output
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=11
|
||||
# At a maximum only compile in this level of debugging
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=11
|
||||
|
||||
# Cheetah Family 10
|
||||
#romimage "normal"
|
||||
# 1MB ROM
|
||||
# option ROM_SIZE = 0x100000
|
||||
# option USE_FAILOVER_IMAGE=0
|
||||
# option USE_FALLBACK_IMAGE=0
|
||||
# option ROM_IMAGE_SIZE=0x20000
|
||||
# option ROM_IMAGE_SIZE=0x30000
|
||||
# option XIP_ROM_SIZE=0x40000
|
||||
# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
|
||||
# payload ../payload.elf
|
||||
#end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FAILOVER_IMAGE=0
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
# option ROM_IMAGE_SIZE=0x13800
|
||||
# option ROM_IMAGE_SIZE=0x19800
|
||||
option ROM_IMAGE_SIZE=0x3f000
|
||||
# option ROM_IMAGE_SIZE=0x15800
|
||||
option XIP_ROM_SIZE=0x40000
|
||||
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "failover"
|
||||
option USE_FAILOVER_IMAGE=1
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=FAILOVER_SIZE
|
||||
option XIP_ROM_SIZE=FAILOVER_SIZE
|
||||
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
|
||||
end
|
||||
|
||||
#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover"
|
||||
buildrom ./amd-cheetah-fam10.rom ROM_SIZE "fallback" "failover"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user