soc/mediatek/mt8192: Add dramc 8 phase calibration
To get better PI linearity, perform 8 phase calibration to do MCK 0/180/45 training and select the best PI settings. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Huayang Duan
committed by
Hung-Te Lin
Hung-Te Lin
parent
4cb885e5be
commit
2d0117e2fe
@@ -3790,6 +3790,7 @@ static void dramc_init(const struct ddr_cali *cali)
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{
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dramc_setting(cali);
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dramc_reset_delay_chain_before_calibration();
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dramc_8_phase_cal(cali);
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}
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static void dramc_before_calibration(const struct ddr_cali *cali)
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@@ -225,3 +225,355 @@ void dramc_sw_impedance_save_register(const struct ddr_cali *cali)
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dramc_set_broadcast(bc_bak);
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}
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static void dramc_phy_reset(u8 chn)
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{
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SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1);
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SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
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SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
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B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0,
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B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0);
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SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
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B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0,
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B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0);
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udelay(1);
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SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
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B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1,
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B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1);
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SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
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B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1,
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B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1);
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SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
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SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0);
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}
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static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back,
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int *ph_dly_final, int *ph_dly_loop_break)
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{
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const u8 early_break_cnt = 5;
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static u8 loop_cnt = 0;
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static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff;
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s16 err_code;
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static s16 err_code_min = 0x7fff;
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u16 dqs_dly;
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const u16 jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1;
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u32 sample_cnt, ones_cnt;
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u8 dqs_level = DQS_LEVEL_UNKNOWN;
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dramc_dbg("8PH dly = %u\n", ph_dly);
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*ph_dly_loop_break = 0;
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SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
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SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly);
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SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
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SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly);
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SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
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SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly);
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for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) {
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/* Set DQS delay */
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SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2,
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B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly);
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SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2,
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B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly);
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dramc_phy_reset(0);
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SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
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MISC_DUTYSCAN1_REG_SW_RST, 1);
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SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
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MISC_DUTYSCAN1_REG_SW_RST, 0);
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SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
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MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
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udelay(10);
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SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
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MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
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sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt,
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MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT);
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ones_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt,
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MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT);
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if (ones_cnt < sample_cnt / 2) {
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if (dqs_level == DQS_LEVEL_UNKNOWN)
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dramc_dbg("[L] %u, %8u\n", dqs_dly, ones_cnt);
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dqs_level = 0;
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} else if (dqs_level == 0) {
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dqs_level = 1;
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dramc_dbg("[H] %u, %8u\n", dqs_dly, ones_cnt);
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if (phase_sm == DQS_8PH_DEGREE_0) {
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r0 = dqs_dly;
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dramc_dbg("R0 = %u\n", r0);
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} else if (phase_sm == DQS_8PH_DEGREE_180) {
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r180 = dqs_dly;
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if (r180 <= r0) {
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dqs_level = DQS_LEVEL_UNKNOWN;
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continue;
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}
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r_tmp = r0 + ((r180 - r0) >> 2);
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dramc_dbg("R = %u, R180 = %u\n", r_tmp, r180);
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} else if (phase_sm == DQS_8PH_DEGREE_45) {
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p_tmp = dqs_dly;
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dramc_dbg("p_tmp = %u, R0 = %u\n", p_tmp, r0);
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if (p_tmp <= r0) {
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dqs_level = DQS_LEVEL_UNKNOWN;
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continue;
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}
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err_code = ABS(p_tmp - r_tmp);
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if (err_code == 0) {
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*ph_dly_final = ph_dly;
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*ph_dly_loop_break = 1;
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} else if (err_code < err_code_min) {
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err_code_min = err_code;
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*ph_dly_final = ph_dly;
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loop_cnt = 0;
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} else {
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loop_cnt++;
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if (loop_cnt > early_break_cnt)
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*ph_dly_loop_break = 1;
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}
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dramc_dbg("diff (P-R) = %d, min = %d, break count = %u\n",
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err_code, err_code_min, loop_cnt);
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} else {
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die("Invalid phase_sm: %u!\n", phase_sm);
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}
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break;
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}
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}
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if (dqs_level == DQS_LEVEL_UNKNOWN || dqs_level == 0) {
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*ph_dly_final = ph_dly_back;
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dramc_err("8-Phase SM_%u failed, falling back to default\n", phase_sm);
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return 0;
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} else if (*ph_dly_loop_break) {
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return -1;
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}
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return -2;
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}
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static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back)
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{
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u8 dqsien_pi;
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u8 phase_sm, ph_dly, ph_start, ph_end;
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int ph_dly_loop_break;
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int ph_dly_final = 0xff; /* default delay: 0xff */
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for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) {
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switch (phase_sm) {
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case DQS_8PH_DEGREE_0:
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dqsien_pi = 16;
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ph_start = 0;
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ph_end = 1;
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break;
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case DQS_8PH_DEGREE_180:
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dqsien_pi = 48;
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ph_start = 0;
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ph_end = 1;
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break;
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case DQS_8PH_DEGREE_45:
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dqsien_pi = 24;
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ph_start = 0;
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ph_end = 32;
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break;
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default:
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die("Invalid phase_sm: %u!\n", phase_sm);
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return;
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}
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dramc_dbg("8-Phase SM_%u, 8PH_dly (%u~%u), DQSIEN PI = %u, 8PH_Dly = %u\n",
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phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back);
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for (u8 rk = RANK_0; rk < cali->support_ranks; rk++)
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SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly,
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SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi);
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for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) {
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int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly,
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ph_dly_back, &ph_dly_final, &ph_dly_loop_break);
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if (ret == 0)
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goto final_found;
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if (ph_dly_loop_break)
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break;
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}
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}
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final_found:
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dramc_dbg("8 phase calibration ph_dly_final = %u\n", ph_dly_final);
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
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SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1,
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SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final);
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SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1,
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SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final);
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SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1,
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SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final);
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}
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}
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void dramc_8_phase_cal(const struct ddr_cali *cali)
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{
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u8 ph_dly_back = 0;
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dram_freq_grp freq_group = cali->freq_group;
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/* ch0 and ch1 of phy_ao */
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struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao;
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struct ddrphy_ao_regs *phy_ao_ch1 = &ch[1].phy_ao;
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if (freq_group < DDRFREQ_2133) {
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dramc_info("Freq %u < 2133, do not need do 8-Phase\n", get_frequency(cali));
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return;
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}
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struct reg_bak regs_bak[] = {
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{&phy_ao->misc_dutyscan1},
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{&phy_ao->dvs_b[0].b0_dq6},
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{&phy_ao->dvs_b[1].b0_dq6},
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{&phy_ao->dvs_b[0].b0_dq5},
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{&phy_ao->dvs_b[1].b0_dq5},
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{&phy_ao->dvs_b[0].b0_dq3},
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{&phy_ao->dvs_b[1].b0_dq3},
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{&phy_ao->misc_ctrl1},
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{&phy_ao->misc_ctrl4},
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{&phy_ao->dvs_b[0].b0_phy2},
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{&phy_ao->dvs_b[1].b0_phy2},
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{&phy_ao->byte[0].shu_b0_dll_arpi2},
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{&phy_ao->byte[1].shu_b0_dll_arpi2},
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{&phy_ao->byte[0].shu_b0_dq11},
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{&phy_ao->byte[1].shu_b0_dq11},
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{&phy_ao->shu_ca_cmd11},
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{&phy_ao->misc_stbcal},
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{&phy_ao->byte[0].rk[0].shu_rk_b0_dqsien_pi_dly},
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{&phy_ao->byte[0].rk[1].shu_rk_b0_dqsien_pi_dly},
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{&phy_ao->misc_jmeter},
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{&phy_ao->misc_shu_stbcal},
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{&phy_ao->shu_ca_dll1},
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{&phy_ao->byte[0].shu_b0_dll1},
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{&phy_ao->byte[1].shu_b0_dll1},
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{&phy_ao->dvs_b[0].b0_dq2},
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{&phy_ao->dvs_b[1].b0_dq2},
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{&phy_ao->ca_cmd2},
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{&phy_ao->byte[0].shu_b0_dq13},
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{&phy_ao->byte[1].shu_b0_dq13},
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{&phy_ao->shu_ca_cmd13},
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{&phy_ao_ch1->shu_ca_dll1},
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{&phy_ao_ch1->byte[0].shu_b0_dll1},
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{&phy_ao_ch1->byte[1].shu_b0_dll1},
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{&phy_ao_ch1->dvs_b[0].b0_dq2},
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{&phy_ao_ch1->dvs_b[1].b0_dq2},
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{&phy_ao_ch1->ca_cmd2},
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{&phy_ao_ch1->byte[0].shu_b0_dq13},
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{&phy_ao_ch1->byte[1].shu_b0_dq13},
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{&phy_ao_ch1->shu_ca_cmd13},
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};
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for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
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regs_bak[i].value = read32(regs_bak[i].addr);
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
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phy_ao = &ch[chn].phy_ao;
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SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq2,
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B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0,
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B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1,
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B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0,
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B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1,
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B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0,
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B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1,
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B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0,
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B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1,
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B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0,
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B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff);
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SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq2,
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B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0,
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B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1,
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B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0,
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B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1,
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B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0,
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B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1,
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B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0,
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B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1,
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B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0,
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B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff);
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SET32_BITFIELDS(&phy_ao->ca_cmd2,
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CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0,
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CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1,
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CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0,
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CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1,
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CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
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CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
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SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq13,
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SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0,
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SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1);
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SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq13,
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SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0,
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SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1);
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SET32_BITFIELDS(&phy_ao->shu_ca_cmd13,
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SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0,
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SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1);
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}
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phy_ao = &ch[0].phy_ao;
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ph_dly_back = READ32_BITFIELD(&phy_ao->byte[0].shu_b0_dq1,
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SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
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SET32_BITFIELDS(&phy_ao->misc_shu_stbcal,
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MISC_SHU_STBCAL_STBCALEN, 0x0,
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MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0);
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SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq11,
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SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0);
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SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq11,
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SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0);
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SET32_BITFIELDS(&phy_ao->shu_ca_cmd11,
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SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0);
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for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
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phy_ao = &ch[chn].phy_ao;
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SET32_BITFIELDS(&phy_ao->shu_ca_dll1,
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SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0,
|
||||
SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0);
|
||||
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll1,
|
||||
SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0,
|
||||
SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0);
|
||||
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll1,
|
||||
SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0,
|
||||
SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0);
|
||||
}
|
||||
|
||||
phy_ao = &ch[0].phy_ao;
|
||||
SET32_BITFIELDS(&phy_ao->misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0);
|
||||
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll_arpi2,
|
||||
SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0);
|
||||
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll_arpi2,
|
||||
SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
|
||||
MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0);
|
||||
SET32_BITFIELDS(&phy_ao->misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq6,
|
||||
B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq6,
|
||||
B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
|
||||
MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1,
|
||||
MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1,
|
||||
MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_jmeter, MISC_JMETER_JMTR_EN, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1);
|
||||
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
|
||||
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0);
|
||||
|
||||
dramc_8_phase_cal_set_best_dly(cali, ph_dly_back);
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
|
||||
write32(regs_bak[i].addr, regs_bak[i].value);
|
||||
}
|
||||
|
||||
@@ -34,6 +34,8 @@
|
||||
#define REG_SHU_OFFSET_WIDTH 0x700
|
||||
#define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4)
|
||||
|
||||
#define DQS_LEVEL_UNKNOWN 0xff
|
||||
|
||||
typedef enum {
|
||||
DDRFREQ_400,
|
||||
DDRFREQ_600,
|
||||
|
||||
Reference in New Issue
Block a user