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soc/intel/alderlake: Remove Alder Lake M SKU

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ADL-M is not commercially available, so it can be removed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Sean Rhodes 2024-02-19 11:47:21 +00:00 committed by Felix Held
parent 9c40215ef2
commit 2eee78aeb4
5 changed files with 2 additions and 33 deletions
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11
src/soc/intel/alderlake/Kconfig
View File

@ -106,12 +106,6 @@ config SOC_INTEL_RAPTORLAKE
Intel Raptorlake support. Mainboards using RPL should select
SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together.
config SOC_INTEL_ALDERLAKE_PCH_M
bool
select SOC_INTEL_ALDERLAKE
help
Choose this option if your mainboard has a PCH-M chipset.
config SOC_INTEL_ALDERLAKE_PCH_N
bool
select HAVE_INTEL_FSP_REPO
@ -244,21 +238,18 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12 if SOC_INTEL_ALDERLAKE_PCH_N
default 12 if SOC_INTEL_ALDERLAKE_PCH_P
default 28 if SOC_INTEL_ALDERLAKE_PCH_S
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S
config MAX_TBT_ROOT_PORTS
int
default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
default 2 if SOC_INTEL_ALDERLAKE_PCH_M
default 4 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
@ -267,7 +258,6 @@ config MAX_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
@ -279,7 +269,6 @@ config MAX_PCIE_CLOCK_SRC
config MAX_PCIE_CLOCK_REQ
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S

2
src/soc/intel/alderlake/acpi/pcie.asl
View File

@ -305,7 +305,7 @@ Device (RP12)
#endif
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)
Device (PEG0)
{
Name (_ADR, 0x00060000)

2
src/soc/intel/alderlake/fsp_params.c
View File

@ -680,9 +680,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
s_cfg->UsbTcPortEn |= BIT(i);
}
#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)
s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
#endif
}
static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,

3
src/soc/intel/alderlake/include/soc/bootblock.h
View File

@ -3,8 +3,7 @@
#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) != 1
#error "Please select exactly one PCH type"

17
src/soc/intel/alderlake/pcie_rp.c
View File

@ -14,12 +14,6 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
{ 0 }
};
static const struct pcie_rp_group pch_m_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 2, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_s_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
@ -30,9 +24,6 @@ static const struct pcie_rp_group pch_s_rp_groups[] = {
const struct pcie_rp_group *get_pch_pcie_rp_table(void)
{
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
return pch_m_rp_groups;
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
return pch_s_rp_groups;
@ -52,11 +43,6 @@ static const struct pcie_rp_group cpu_rp_groups[] = {
{ 0 }
};
static const struct pcie_rp_group cpu_m_rp_groups[] = {
{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group cpu_n_rp_groups[] = {
{ 0 }
};
@ -69,9 +55,6 @@ static const struct pcie_rp_group cpu_s_rp_groups[] = {
const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
{
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
return cpu_m_rp_groups;
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N))
return cpu_n_rp_groups;