BDI2000 config file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
c72e27616d
commit
2f2e63bc7d
89
src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
Executable file
89
src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
Executable file
@ -0,0 +1,89 @@
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; bdiGDB configuration file for the Embedded Planet EP405PC
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; ---------------------------------------------------------
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;
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[INIT]
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; init core register
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WSPR 954 0x00000000 ;DCWR: Disable data cache write-thru
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WSPR 1018 0x00000000 ;DCCR: Disable data cache
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WSPR 1019 0x00000000 ;ICCR: Disable instruction cache
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WSPR 981 0x00000000 ;EVPR: Exception Vector Table @0x00000000
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; Setup SDRAM Controller
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WDCR 16 0x00000080 ;Select SDRAM0_TR
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WDCR 17 0x010E8016 ;TR: SDRAM Timing Register
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WDCR 16 0x00000040 ;Select SDRAM0_B0CR
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WDCR 17 0x00084001 ;Select bank 0
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WDCR 16 0x00000030 ;Select SDRAM0_RTR
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WDCR 17 0x08080000 ;RTR: Refresh Timing Register
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WDCR 16 0x00000094 ;Select SDRAM0_ECCCFG
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WDCR 17 0x00000000 ;ECC: Disabled
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WDCR 16 0x00000034 ;Select SDRAM0_PMIT
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WDCR 17 0x0F000000 ;PMIT: Power Management Idle Timer
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DELAY 1 ;Wait for SDRAM powerup
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WDCR 16 0x00000020 ;Select SDRAM0_CFG
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WDCR 17 0x80C00000 ;CFG: Enable
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; MMU
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WM32 0xf0 0x00000000 ;invalidate page table base
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; EBC
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WDCR 0x12 0x00000004 ;Select EBC0_B4CR
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WDCR 0x13 0xF4058000 ;Set NVRTC/BCSR
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WDCR 0x12 0x00000014 ;Select EBC0_B4AP
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WDCR 0x13 0x04050000 ;Set NVRTC/BCSR timing
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WM8 0xF4000003 0x20 ;Enable UART0
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WM8 0xF4000009 0x07 ;LED
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DELAY 500
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WM8 0xF4000009 0x0b ;LED
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DELAY 500
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WM8 0xF4000009 0x0d ;LED
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DELAY 500
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WM8 0xF4000009 0x0e ;LED
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DELAY 500
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[TARGET]
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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CPUTYPE 405 ;the used target CPU type
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BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT)
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;WAKEUP 3000 ;wakeup time after reset
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints
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VECTOR CATCH ;catch unhandled exceptions
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MMU XLAT 0xC0000000 ;enable virtual address mode
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PTBASE 0x000000f0 ;address where kernel/user stores pointer to page table
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SIO 2002 9600 ;TCP port for serial IO
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;SIO 2002 115200 ;TCP port for serial IO
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;REGLIST SPR ;select register to transfer to GDB
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;REGLIST ALL ;select register to transfer to GDB
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;SCANPRED 2 2 ;JTAG devices connected before PPC400
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;SCANSUCC 3 3 ;JTAG devices connected after PPC400
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[HOST]
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IP 10.0.1.2
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FORMAT ELF
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FILE linuxbios.elf
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;START 0x200000
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LOAD MANUAL ;load code MANUAL or AUTO after reset
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DEBUGPORT 2001
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DUMP dump.bin ;Linux: dump.bin must already exist and public writable
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[FLASH]
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WORKSPACE 0x00004000 ;workspace in target RAM for fast programming algorithm
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CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
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CHIPSIZE 0x400000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
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BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32)
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ERASE 0xFFF80000 ;erase sector 0 of flash in U7 (AM29F040)
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ERASE 0xFFF90000 ;erase sector 1 of flash
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ERASE 0xFFFA0000 ;erase sector 2 of flash
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ERASE 0xFFFB0000 ;erase sector 3 of flash
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ERASE 0xFFFC0000 ;erase sector 4 of flash
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ERASE 0xFFFD0000 ;erase sector 5 of flash
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ERASE 0xFFFE0000 ;erase sector 6 of flash
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ERASE 0xFFFF0000 ;erase sector 7 of flash
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[REGS]
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IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA
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IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA
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IDCR3 0x014 0x015 ;KIAR and KIDR
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FILE reg405gp.def
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139
src/mainboard/motorola/sandpoint/sp7410.cfg
Normal file
139
src/mainboard/motorola/sandpoint/sp7410.cfg
Normal file
@ -0,0 +1,139 @@
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; bdiGDB configuration file for the Sandpoint X3 evaluation system
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; with the Altimus 7410 PMC
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;-----------------------------------------------------------------
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;
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[INIT]
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; init core register
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WREG MSR 0x00000000 ;clear MSR
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;
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; init memory controller (based on DINK32)
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WM32 0xFEC00000 0x46000080 ;select PCIARB
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WM16 0xFEE00002 0x0080 ;
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WM32 0xFEC00000 0x73000080 ;select ODCR
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WM8 0xFEE00003 0xd1 ;
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WM32 0xFEC00000 0x74000080 ;select CDCR
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WM16 0xFEE00000 0x00fd ;
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WM32 0xFEC00000 0x76000080 ;select MICR
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WM8 0xFEE00002 0x40 ;
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WM32 0xFEC00000 0x80000080 ;select MSAR1
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WM32 0xFEE00000 0x0080a0c0 ;
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WM32 0xFEC00000 0x84000080 ;select MSAR2
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WM32 0xFEE00000 0xe0002040 ;
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WM32 0xFEC00000 0x88000080 ;select MSAR3
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WM32 0xFEE00000 0x00000000 ;
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WM32 0xFEC00000 0x8c000080 ;select MSAR4
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WM32 0xFEE00000 0x00010101 ;
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WM32 0xFEC00000 0x90000080 ;select MEAR1
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WM32 0xFEE00000 0x7f9fbfdf ;
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WM32 0xFEC00000 0x94000080 ;select MEAR2
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WM32 0xFEE00000 0xff1f3f5f ;
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WM32 0xFEC00000 0x98000080 ;select MEAR3
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WM32 0xFEE00000 0x00000000 ;
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WM32 0xFEC00000 0x9c000080 ;select MEAR4
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WM32 0xFEE00000 0x00010101 ;
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WM32 0xFEC00000 0xa0000080 ;select MBEN
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WM8 0xFEE00000 0x01 ;
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WM32 0xFEC00000 0xa3000080 ;select PGMAX
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WM8 0xFEE00003 0x32 ;
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WM32 0xFEC00000 0xa8000080 ;select PIC1
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WM32 0xFEE00000 0x981a14ff ;
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WM32 0xFEC00000 0xac000080 ;select PIC2
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WM32 0xFEE00000 0x00000004 ;
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WM32 0xFEC00000 0xe0000080 ;select AMBOR
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WM8 0xFEE00000 0xc0 ;
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WM32 0xFEC00000 0xf0000080 ;select MCCR1
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WM32 0xFEE00000 0xaaaae075 ;do not set MEMGO
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WM32 0xFEC00000 0xf4000080 ;select MCCR2
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WM32 0xFEE00000 0x2c184004 ;
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WM32 0xFEC00000 0xf8000080 ;select MCCR3
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WM32 0xFEE00000 0x00003078 ;
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WM32 0xFEC00000 0xfc000080 ;select MCCR4
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WM32 0xFEE00000 0x39223235 ;
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DELAY 100
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WM32 0xFEC00000 0xf0000080 ;select MCCR1
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WM32 0xFEE00000 0xaaaae875 ;now set MEMGO
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;
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WM32 0xFEC00000 0x78000080 ;select EUMBBAR
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WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000
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;
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;WM32 0xFEC00000 0xa8000080 ;select PICR1
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;WM32 0xFEE00000 0x901014ff ;enable flash write (Flash on processor bus)
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;
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; Enable UART0
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;
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WM8 0xFE00015C 0x07
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WM8 0xFE00015D 0x06
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WM8 0xFE00015C 0x30
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WM8 0xFE00015D 0x00
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WM8 0xFE00015C 0x60
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WM8 0xFE00015D 0x03
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WM8 0xFE00015C 0x61
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WM8 0xFE00015D 0xf8
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WM8 0xFE00015C 0x30
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WM8 0xFE00015D 0x01
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;
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; define maximal transfer size
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;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM)
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TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash)
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[TARGET]
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CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400)
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush
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BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY)
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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;STEPMODE HWBP ;TRACE or HWBP, HWPB uses a hardware breakpoint
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;VECTOR CATCH ;catch unhandled exceptions
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DCACHE NOFLUSH ;data cache flushing (FLUSH | NOFLUSH)
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;PARITY ON ;enable data parity generation
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MEMDELAY 400 ;additional memory access delay
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;REGLIST STD ;select register to transfer to GDB
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;L2PM 0x00100000 0x80000 ;L2 privat memory
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;SIO 2002 115200
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SIO 2002 9600
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;MMU XLAT
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;PTBASE 0x000000f0
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[HOST]
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IP 10.0.1.11
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;FILE E:\cygnus\root\usr\demo\sp7400\vxworks
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FILE linuxbios.elf
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FORMAT ELF
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;START 0x403104
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LOAD MANUAL ;load code MANUAL or AUTO after reset
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DEBUGPORT 2001
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[FLASH]
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; Am29LV800BB on local processor bus (RCS0)
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; set PPMC7410 switch SW2-1 OFF => ROM on Local bus
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; enable flash write in PICR1 (see INIT part)
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; set maximal transfer size to 4 bytes (see INIT part)
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CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
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CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
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BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
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WORKSPACE 0x00000000 ;workspace in SDRAM
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FILE linuxbios.elf
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FORMAT ELF
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ERASE 0xFFF00000 ;erase sector 0 of flash
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ERASE 0xFFF04000 ;erase sector 1 of flash
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ERASE 0xFFF06000 ;erase sector 2 of flash
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ERASE 0xFFF08000 ;erase sector 3 of flash
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ERASE 0xFFF10000 ;erase sector 4 of flash
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ERASE 0xFFF20000 ;erase sector 5 of flash
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ERASE 0xFFF30000 ;erase sector 6 of flash
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ERASE 0xFFF40000 ;erase sector 7 of flash
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ERASE 0xFFF50000 ;erase sector 8 of flash
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ERASE 0xFFF60000 ;erase sector 9 of flash
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ERASE 0xFFF70000 ;erase sector 10 of flash
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[REGS]
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DMM1 0xFC000000 ;Embedded utility memory base address
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IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0
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IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1
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IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2
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IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3
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FILE mpc107.def
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178
src/mainboard/totalimpact/briq/briQ7400.cfg
Normal file
178
src/mainboard/totalimpact/briq/briQ7400.cfg
Normal file
@ -0,0 +1,178 @@
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; bdiGDB configuration file for briQ (http://www.totalimpact.com)
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; ---------------------------------------------------------------
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;
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; NOTE: As of June 2004, you will need to install a pull-down
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; on the COP/JTAG QACK line. Without this, the BDI2000
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; is not able to halt the CPU
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; (http://www.ultsol.com/faq-P210.htm)
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;
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[INIT]
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; init core register
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WREG MSR 0x00000000 ;clear MSR
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;
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; init CPC710
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;
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WM32 0xFF000010 0xF0000000 ; RSTR
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WM32 0xFF001020 0x00000000 ; SIOC
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WM32 0xFF001000 0x00780000 ; UCTL (resID=7|TBE)
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WM32 0xFF001030 0x00000000 ; ABCNTL
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WM32 0xFF001040 0x00000000 ; SRST
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WM32 0xFF001050 0x00000000 ; ERRC
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WM32 0xFF001060 0x00000000 ; SESR
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WM32 0xFF001070 0x00000000 ; SEAR
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WM32 0xFF001100 0x000000E0 ; PGCHP (PReP|ARTRY|750|SYS_TEA)
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WM32 0xFF001130 0x40000000 ; GPDIR
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WM32 0xFF001150 0x40000000 ; GPOUT
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WM32 0xFF001160 0x709C2508 ; ATAS
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WM32 0xFF001170 0x00000000 ; AVDG
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WM32 0xFF001220 0x00000000 ; MESR
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WM32 0xFF001230 0x00000000 ; MEAR
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WM32 0xFF001210 0x00000000 ; MWPR
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WM32 0xFF001120 0x00000000 ; RGBAN1
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;
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; init memory - this assumes 2 x 512MB DIMMs
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;
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WM32 0xFF001300 0x80000080 ; MCER0
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WM32 0xFF001310 0x82000080 ; MCER1
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WM32 0xFF001320 0x00000000 ; MCER2
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WM32 0xFF001330 0x00000000 ; MCER3
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WM32 0xFF001340 0x00000000 ; MCER4
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WM32 0xFF001350 0x00000000 ; MCER5
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WM32 0xFF001200 0xD2B06000 ; MCCR
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DELAY 1000
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;
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; enable pci
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;
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WM32 0xFF00000C 0x80000002 ; CNFR
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WM32 0xFF200018 0xFF500000 ; PCIBAR
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WM32 0xFF201000 0x80000000 ; PCIENB
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WM32 0xFF00000C 0x00000000 ; CNFR
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;
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; config pci
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;
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WM32 0xFF5F8000 0x06000080
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WM16 0xFF5F8010 0xFFFF
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WM32 0xFF5F8000 0x40000080
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WM16 0xFF5F8010 0x0000
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WM32 0xFF5F6120 0x40000000 ; PCIDG
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WM32 0xFF5F7800 0x00000000 ; PIBAR
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WM32 0xFF5F7810 0x00000000 ; PMBAR
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WM32 0xFF5F7F20 0xA000C000 ; PR
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WM32 0xFF5F7F30 0xFC000000 ; ACR
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WM32 0xFF5F7F40 0xF8000000 ; MSIZE
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WM32 0xFF5F7F60 0xF8000000 ; IOSIZE
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WM32 0xFF5F7F80 0xC0000000 ; SMBAR
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WM32 0xFF5F7FC0 0x80000000 ; SIBAR
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WM32 0xFF5F8100 0x00000080 ; PSSIZE
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WM32 0xFF5F8120 0x00000000 ; BARPS
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WM32 0xFF5F8140 0x00000080 ; PSBAR
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WM32 0xFF5F8200 0x00000000 ; BPMDLK
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WM32 0xFF5F8210 0x00000000 ; TPMDLK
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WM32 0xFF5F8220 0x00000000 ; BIODLK
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WM32 0xFF5F8230 0x00000000 ; TIODLK
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WM32 0xFF5F8000 0x04000080
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WM16 0xFF5F8010 0xA7FD
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WM32 0xFF5F7EF0 0xFC000000 ; CRR
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;
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; VFD - output the sequence '01234' to show
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; something is happening
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;
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;WM8 0x80000390 0x38
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;WM8 0x80000390 0x01
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;WM8 0x80000390 0x0C
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;WM8 0x80000390 0x06
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;WM8 0x80000390 0x02
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;DELAY 100
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;WM8 0x80000391 0x30
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;DELAY 100
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;WM8 0x80000391 0x31
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;DELAY 100
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;WM8 0x80000391 0x32
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;DELAY 100
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;WM8 0x80000391 0x33
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;DELAY 100
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;WM8 0x80000391 0x34
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;
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; UART - output the sequence '01234' to show
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; something is happening
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;
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WM8 0x800003F9 0
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WM8 0x800003FA 1
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WM8 0x800003FB 0x83
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WM8 0x800003F8 4 ; 115200
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WM8 0x800003F9 0
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WM8 0x800003FB 0x3
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DELAY 100
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WM8 0x800003F8 0x30
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DELAY 100
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WM8 0x800003F8 0x31
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DELAY 100
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WM8 0x800003F8 0x32
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DELAY 100
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WM8 0x800003F8 0x33
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DELAY 100
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WM8 0x800003F8 0x34
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;
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; define maximal transfer size
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;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM)
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TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash)
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[TARGET]
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CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400)
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush
|
||||
BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY)
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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STEPMODE TRACE ;TRACE or HWBP, HWPB uses a hardware breakpoint
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;VECTOR CATCH ;catch unhandled exceptions
|
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DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH)
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;PARITY ON ;enable data parity generation
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;MEMDELAY 4000 ;additional memory access delay
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;REGLIST STD ;select register to transfer to GDB
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;L2PM 0x00100000 0x80000 ;L2 privat memory
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BOOTADDR 0xfff00100
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STARTUP RESET
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[HOST]
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FORMAT ELF
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LOAD MANUAL ;load code MANUAL or AUTO after reset
|
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DEBUGPORT 2001
|
||||
|
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[FLASH]
|
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; Am29LV800BB on local processor bus (RCS0)
|
||||
; set PPMC7410 switch SW2-1 OFF => ROM on Local bus
|
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; enable flash write in PICR1 (see INIT part)
|
||||
; set maximal transfer size to 4 bytes (see INIT part)
|
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CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
|
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CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
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BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
|
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;WORKSPACE 0x00000000 ;workspace in SDRAM
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FILE linuxbios.rom
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FORMAT ELF
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ERASE 0xFFF00000 ;erase sector 0 of flash
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ERASE 0xFFF10000 ;erase sector 1 of flash
|
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ERASE 0xFFF20000 ;erase sector 2 of flash
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ERASE 0xFFF30000 ;erase sector 3 of flash
|
||||
ERASE 0xFFF40000 ;erase sector 4 of flash
|
||||
ERASE 0xFFF50000 ;erase sector 5 of flash
|
||||
ERASE 0xFFF60000 ;erase sector 6 of flash
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ERASE 0xFFF70000 ;erase sector 7 of flash
|
||||
;ERASE 0xFFF80000 ;erase sector 8 of flash
|
||||
;ERASE 0xFFF90000 ;erase sector 9 of flash
|
||||
;ERASE 0xFFFA0000 ;erase sector 10 of flash
|
||||
;ERASE 0xFFFB0000 ;erase sector 11 of flash
|
||||
;ERASE 0xFFFC0000 ;erase sector 12 of flash
|
||||
;ERASE 0xFFFD0000 ;erase sector 13 of flash
|
||||
;ERASE 0xFFFE0000 ;erase sector 14 of flash
|
||||
;ERASE 0xFFFF0000 ;erase sector 15 of flash
|
||||
|
||||
[REGS]
|
||||
;DMM1 0xFC000000 ;Embedded utility memory base address
|
||||
;IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0
|
||||
;IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1
|
||||
;IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2
|
||||
;IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3
|
||||
FILE cpc700.def
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user