soc/intel/skylake: Extract fsp_params.c out of romstage.c
Done for consistency with newer platforms. Also clean up includes. Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
53496e69ec
commit
3157068bf8
@ -1,3 +1,4 @@
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romstage-y += fsp_params.c
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romstage-y += ../../../../cpu/intel/car/romstage.c
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romstage-y += ../../../../cpu/intel/car/romstage.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += systemagent.c
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romstage-y += systemagent.c
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189
src/soc/intel/skylake/romstage/fsp_params.c
Normal file
189
src/soc/intel/skylake/romstage/fsp_params.c
Normal file
@ -0,0 +1,189 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/soc_chip.h>
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static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
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{
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msr_t flex_ratio;
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m_cfg->CpuRatioOverride = 1;
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/*
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* Set cpuratio to that value set in bootblock, This will ensure FSPM
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* knows the intended flex ratio.
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*/
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flex_ratio = rdmsr(MSR_FLEX_RATIO);
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m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
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}
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static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
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FSP_M_TEST_CONFIG *m_t_cfg,
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const struct soc_intel_skylake_config *config)
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{
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const struct device *dev;
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/*
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* To enable or disable the corresponding PEG root port you need to
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* add to the devicetree.cb:
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*
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* device pci 01.0 on end # enable PEG0 root port
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* device pci 01.1 off end # do not configure PEG1
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*
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* If PEG port is not defined in the device tree, it will be disabled
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* in FSP
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*/
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dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
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m_cfg->Peg0Enable = dev && dev->enabled;
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if (m_cfg->Peg0Enable) {
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m_cfg->Peg0Enable = 2;
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m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
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/* Use maximum possible link speed */
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m_cfg->Peg0MaxLinkSpeed = 0;
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/* Power down unused lanes based on the max possible width */
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m_cfg->Peg0PowerDownUnusedLanes = 1;
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/* Set [Auto] for options to enable equalization methods */
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m_t_cfg->Peg0Gen3EqPh2Enable = 2;
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m_t_cfg->Peg0Gen3EqPh3Method = 0;
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}
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dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
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m_cfg->Peg1Enable = dev && dev->enabled;
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if (m_cfg->Peg1Enable) {
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m_cfg->Peg1Enable = 2;
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m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
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m_cfg->Peg1MaxLinkSpeed = 0;
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m_cfg->Peg1PowerDownUnusedLanes = 1;
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m_t_cfg->Peg1Gen3EqPh2Enable = 2;
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m_t_cfg->Peg1Gen3EqPh3Method = 0;
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}
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dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
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m_cfg->Peg2Enable = dev && dev->enabled;
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if (m_cfg->Peg2Enable) {
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m_cfg->Peg2Enable = 2;
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m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
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m_cfg->Peg2MaxLinkSpeed = 0;
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m_cfg->Peg2PowerDownUnusedLanes = 1;
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m_t_cfg->Peg2Gen3EqPh2Enable = 2;
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m_t_cfg->Peg2Gen3EqPh3Method = 0;
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}
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}
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_skylake_config *config)
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{
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int i;
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uint32_t mask = 0;
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m_cfg->MmioSize = 0x800; /* 2GB in MB */
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
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m_cfg->ProbelessTrace = 0;
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m_cfg->SaGv = config->SaGv;
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m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
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m_cfg->RMT = config->Rmt;
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m_cfg->CmdTriStateDis = config->CmdTriStateDis;
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m_cfg->DdrFreqLimit = 0;
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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m_cfg->PrmrrSize = get_valid_prmrr_size();
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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if (config->PcieRpEnable[i])
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mask |= (1<<i);
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}
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m_cfg->PcieRpEnableMask = mask;
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cpu_flex_override(m_cfg);
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/* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */
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m_cfg->PchHpetBdfValid = 0;
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m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING);
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}
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static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_skylake_config *config)
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{
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const struct device *dev;
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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m_cfg->InternalGfx = dev && dev->enabled;
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/*
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* If iGPU is enabled, set IGD stolen size to 64MB. The FBC
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* hardware for skylake does not have access to the bios
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* reserved range so it always assumes 8MB is used and so the
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* kernel will avoid the last 8MB of the stolen window. With
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* the default stolen size of 32MB(-8MB) there is not enough
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* space for FBC to work with a high resolution panel.
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*
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* If disabled, don't reserve memory for it.
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*/
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m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0;
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m_cfg->PrimaryDisplay = config->PrimaryDisplay;
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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const struct soc_intel_skylake_config *config;
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const struct device *dev;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
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config = config_of_soc();
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soc_memory_init_params(m_cfg, config);
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soc_peg_init_params(m_cfg, m_t_cfg, config);
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/* Skip creating Management Engine MBP HOB */
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m_t_cfg->SkipMbpHob = 0x01;
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/* Enable DMI Virtual Channel for ME */
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m_t_cfg->DmiVcm = 0x01;
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/* Enable Sending DID to ME */
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m_t_cfg->SendDidMsg = 0x01;
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m_t_cfg->DidInitStat = 0x01;
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/* DCI and TraceHub configs */
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m_t_cfg->PchDciEn = config->PchDciEn;
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dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
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m_cfg->EnableTraceHub = dev && dev->enabled;
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m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
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m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
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/* Enable SMBus controller */
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dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
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m_cfg->SmbusEnable = dev && dev->enabled;
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/* Set primary graphic device */
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soc_primary_gfx_config_params(m_cfg, config);
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m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;
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mainboard_memory_init_params(mupd);
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}
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void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
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struct mma_config_param *mma_cfg)
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{
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/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
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assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
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memory_cfg->MmaTestContentPtr =
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(uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
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memory_cfg->MmaTestContentSize =
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region_device_sz(&mma_cfg->test_content);
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memory_cfg->MmaTestConfigPtr =
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(uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
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memory_cfg->MmaTestConfigSize =
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region_device_sz(&mma_cfg->test_param);
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memory_cfg->MrcFastBoot = 0x00;
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memory_cfg->SaGv = 0x02;
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}
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@ -1,28 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <arch/romstage.h>
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#include <arch/symbols.h>
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#include <assert.h>
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#include <cpu/x86/msr.h>
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#include <cbmem.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smbus.h>
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#include <intelblocks/smbus.h>
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#include <memory_info.h>
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#include <memory_info.h>
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#include <smbios.h>
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#include <smbios.h>
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#include <soc/intel/common/smbios.h>
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#include <soc/intel/common/smbios.h>
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#include <soc/msr.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/systemagent.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#include <string.h>
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#include <security/vboot/vboot_common.h>
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#include "../chip.h"
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#define FSP_SMBIOS_MEMORY_INFO_GUID \
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#define FSP_SMBIOS_MEMORY_INFO_GUID \
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{ \
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{ \
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@ -142,180 +134,3 @@ void mainboard_romstage_entry(void)
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if (!s3wake)
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if (!s3wake)
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save_dimm_info();
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save_dimm_info();
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}
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}
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static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
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{
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msr_t flex_ratio;
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m_cfg->CpuRatioOverride = 1;
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/*
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* Set cpuratio to that value set in bootblock, This will ensure FSPM
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* knows the intended flex ratio.
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*/
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flex_ratio = rdmsr(MSR_FLEX_RATIO);
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m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
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}
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static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
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FSP_M_TEST_CONFIG *m_t_cfg,
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const struct soc_intel_skylake_config *config)
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{
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const struct device *dev;
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/*
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* To enable or disable the corresponding PEG root port you need to
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* add to the devicetree.cb:
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*
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* device pci 01.0 on end # enable PEG0 root port
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* device pci 01.1 off end # do not configure PEG1
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*
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* If PEG port is not defined in the device tree, it will be disabled
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* in FSP
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*/
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dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
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m_cfg->Peg0Enable = dev && dev->enabled;
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if (m_cfg->Peg0Enable) {
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m_cfg->Peg0Enable = 2;
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m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
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/* Use maximum possible link speed */
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m_cfg->Peg0MaxLinkSpeed = 0;
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/* Power down unused lanes based on the max possible width */
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m_cfg->Peg0PowerDownUnusedLanes = 1;
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/* Set [Auto] for options to enable equalization methods */
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m_t_cfg->Peg0Gen3EqPh2Enable = 2;
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m_t_cfg->Peg0Gen3EqPh3Method = 0;
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}
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dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
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m_cfg->Peg1Enable = dev && dev->enabled;
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if (m_cfg->Peg1Enable) {
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m_cfg->Peg1Enable = 2;
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m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
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m_cfg->Peg1MaxLinkSpeed = 0;
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m_cfg->Peg1PowerDownUnusedLanes = 1;
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m_t_cfg->Peg1Gen3EqPh2Enable = 2;
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m_t_cfg->Peg1Gen3EqPh3Method = 0;
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}
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dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
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m_cfg->Peg2Enable = dev && dev->enabled;
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if (m_cfg->Peg2Enable) {
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m_cfg->Peg2Enable = 2;
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m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
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m_cfg->Peg2MaxLinkSpeed = 0;
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m_cfg->Peg2PowerDownUnusedLanes = 1;
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m_t_cfg->Peg2Gen3EqPh2Enable = 2;
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m_t_cfg->Peg2Gen3EqPh3Method = 0;
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}
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}
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_skylake_config *config)
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{
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int i;
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uint32_t mask = 0;
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m_cfg->MmioSize = 0x800; /* 2GB in MB */
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
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m_cfg->ProbelessTrace = 0;
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m_cfg->SaGv = config->SaGv;
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m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
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m_cfg->RMT = config->Rmt;
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m_cfg->CmdTriStateDis = config->CmdTriStateDis;
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m_cfg->DdrFreqLimit = 0;
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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m_cfg->PrmrrSize = get_valid_prmrr_size();
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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if (config->PcieRpEnable[i])
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mask |= (1<<i);
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}
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m_cfg->PcieRpEnableMask = mask;
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cpu_flex_override(m_cfg);
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/* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */
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m_cfg->PchHpetBdfValid = 0;
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m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING);
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}
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static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
|
|
||||||
const struct soc_intel_skylake_config *config)
|
|
||||||
{
|
|
||||||
const struct device *dev;
|
|
||||||
|
|
||||||
dev = pcidev_path_on_root(SA_DEVFN_IGD);
|
|
||||||
m_cfg->InternalGfx = dev && dev->enabled;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If iGPU is enabled, set IGD stolen size to 64MB. The FBC
|
|
||||||
* hardware for skylake does not have access to the bios
|
|
||||||
* reserved range so it always assumes 8MB is used and so the
|
|
||||||
* kernel will avoid the last 8MB of the stolen window. With
|
|
||||||
* the default stolen size of 32MB(-8MB) there is not enough
|
|
||||||
* space for FBC to work with a high resolution panel.
|
|
||||||
*
|
|
||||||
* If disabled, don't reserve memory for it.
|
|
||||||
*/
|
|
||||||
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0;
|
|
||||||
|
|
||||||
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
|
|
||||||
}
|
|
||||||
|
|
||||||
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
|
|
||||||
{
|
|
||||||
const struct soc_intel_skylake_config *config;
|
|
||||||
const struct device *dev;
|
|
||||||
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
|
|
||||||
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
|
|
||||||
|
|
||||||
config = config_of_soc();
|
|
||||||
|
|
||||||
soc_memory_init_params(m_cfg, config);
|
|
||||||
soc_peg_init_params(m_cfg, m_t_cfg, config);
|
|
||||||
|
|
||||||
/* Skip creating Management Engine MBP HOB */
|
|
||||||
m_t_cfg->SkipMbpHob = 0x01;
|
|
||||||
|
|
||||||
/* Enable DMI Virtual Channel for ME */
|
|
||||||
m_t_cfg->DmiVcm = 0x01;
|
|
||||||
|
|
||||||
/* Enable Sending DID to ME */
|
|
||||||
m_t_cfg->SendDidMsg = 0x01;
|
|
||||||
m_t_cfg->DidInitStat = 0x01;
|
|
||||||
|
|
||||||
/* DCI and TraceHub configs */
|
|
||||||
m_t_cfg->PchDciEn = config->PchDciEn;
|
|
||||||
|
|
||||||
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
|
|
||||||
m_cfg->EnableTraceHub = dev && dev->enabled;
|
|
||||||
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
|
|
||||||
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
|
|
||||||
|
|
||||||
/* Enable SMBus controller */
|
|
||||||
dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
|
|
||||||
m_cfg->SmbusEnable = dev && dev->enabled;
|
|
||||||
|
|
||||||
/* Set primary graphic device */
|
|
||||||
soc_primary_gfx_config_params(m_cfg, config);
|
|
||||||
m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;
|
|
||||||
|
|
||||||
mainboard_memory_init_params(mupd);
|
|
||||||
}
|
|
||||||
|
|
||||||
void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
|
|
||||||
struct mma_config_param *mma_cfg)
|
|
||||||
{
|
|
||||||
/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
|
|
||||||
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
|
|
||||||
|
|
||||||
memory_cfg->MmaTestContentPtr =
|
|
||||||
(uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
|
|
||||||
memory_cfg->MmaTestContentSize =
|
|
||||||
region_device_sz(&mma_cfg->test_content);
|
|
||||||
memory_cfg->MmaTestConfigPtr =
|
|
||||||
(uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
|
|
||||||
memory_cfg->MmaTestConfigSize =
|
|
||||||
region_device_sz(&mma_cfg->test_param);
|
|
||||||
memory_cfg->MrcFastBoot = 0x00;
|
|
||||||
memory_cfg->SaGv = 0x02;
|
|
||||||
}
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user