soc/intel: Drop romstage_pch_init() function

It only calls `smbus_common_init()`, so just call that directly.

Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/include/soc/romstage.h

@@ -8,7 +8,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/alderlake/romstage/Makefile.inc

@@ -3,5 +3,4 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
-romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/alderlake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBus base address and enable it */
-	smbus_common_init();
-}

src/soc/intel/alderlake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -120,8 +121,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Perform PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* Initialize HECI interface */
 	heci_init(HECI1_BASE_ADDRESS);
 

src/soc/intel/cannonlake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/cannonlake/romstage/Makefile.inc

@@ -4,4 +4,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += fsp_params.c
 romstage-y += systemagent.c
-romstage-y += pch.c

src/soc/intel/cannonlake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and enable it */
-	smbus_common_init();
-}

src/soc/intel/cannonlake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -121,8 +122,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 

src/soc/intel/elkhartlake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/elkhartlake/romstage/Makefile.inc

@@ -3,5 +3,4 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
-romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/elkhartlake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-}

src/soc/intel/elkhartlake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -127,8 +128,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 

src/soc/intel/icelake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/icelake/romstage/Makefile.inc

@@ -3,5 +3,4 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
-romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/icelake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-}

src/soc/intel/icelake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -110,8 +111,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 

src/soc/intel/jasperlake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/jasperlake/romstage/Makefile.inc

@@ -3,5 +3,4 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
-romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/jasperlake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-}

src/soc/intel/jasperlake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -127,8 +128,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 

src/soc/intel/skylake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/skylake/romstage/Makefile.inc

@@ -1,4 +1,3 @@
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
-romstage-y += pch.c

src/soc/intel/skylake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and enable it */
-	smbus_common_init();
-}

src/soc/intel/skylake/romstage/romstage.c

@@ -10,6 +10,7 @@
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <smbios.h>
 #include <soc/intel/common/smbios.h>
@@ -132,8 +133,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	ps = pmc_get_power_state();
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);

src/soc/intel/tigerlake/include/soc/romstage.h

@@ -7,7 +7,6 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/tigerlake/romstage/Makefile.inc

@@ -3,5 +3,4 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
-romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/tigerlake/romstage/pch.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-}

src/soc/intel/tigerlake/romstage/romstage.c

@@ -7,6 +7,7 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -127,8 +128,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-	/* Program PCH init */
-	romstage_pch_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);