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Braswell: Add Braswell SOC support

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Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2015-04-20 15:20:28 -07:00
committed by Leroy P Leahy
parent 5fe62efb77
commit 32471729d9
94 changed files with 3688 additions and 5359 deletions
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144
src/soc/intel/braswell/chip.h
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@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,46 +18,28 @@
* Foundation, Inc.
*/
/* The devicetree parser expects chip.h to reside directly in the path
* specified by the devicetree. */
/*
* The devicetree parser expects chip.h to reside directly in the path
* specified by the devicetree.
*/
#ifndef _BAYTRAIL_CHIP_H_
#define _BAYTRAIL_CHIP_H_
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <stdint.h>
#include <fsp_util.h>
#include <soc/pci_devs.h>
struct soc_intel_baytrail_config {
#define SVID_CONFIG1 1
#define SVID_CONFIG3 3
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t sata_port_map;
uint8_t sata_ahci;
uint8_t ide_legacy_combined;
uint8_t clkreq_enable;
/* VR low power settings -- enable PS2 mode for gfx and core */
int vnn_ps2_enable;
int vcc_ps2_enable;
/* Disable SLP_X stretching after SUS power well loss. */
int disable_slp_x_stretch_sus_fail;
/* USB Port Disable mask */
uint16_t usb2_port_disable_mask;
uint16_t usb3_port_disable_mask;
/* USB routing */
int usb_route_to_xhci;
/* USB PHY settings specific to the board */
uint32_t usb2_per_port_lane0;
uint32_t usb2_per_port_rcomp_hs_pullup0;
uint32_t usb2_per_port_lane1;
uint32_t usb2_per_port_rcomp_hs_pullup1;
uint32_t usb2_per_port_lane2;
uint32_t usb2_per_port_rcomp_hs_pullup2;
uint32_t usb2_per_port_lane3;
uint32_t usb2_per_port_rcomp_hs_pullup3;
uint32_t usb2_comp_bg;
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */
int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
@@ -67,29 +50,94 @@ struct soc_intel_baytrail_config {
/* Enable devices in ACPI mode */
int lpss_acpi_mode;
int scc_acpi_mode;
int emmc_acpi_mode;
int sd_acpi_mode;
int lpe_acpi_mode;
/* Allow PCIe devices to wake system from suspend. */
int pcie_wake_enable;
int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
uint16_t gpu_pipea_power_on_delay;
uint16_t gpu_pipea_light_on_delay;
uint16_t gpu_pipea_power_off_delay;
uint16_t gpu_pipea_light_off_delay;
uint16_t gpu_pipea_power_cycle_delay;
int gpu_pipea_pwm_freq_hz;
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during
* MemoryInit.
*/
UINT16 PcdMrcInitTsegSize;
UINT16 PcdMrcInitMmioSize;
UINT8 PcdMrcInitSpdAddr1;
UINT8 PcdMrcInitSpdAddr2;
UINT8 PcdIgdDvmt50PreAlloc;
UINT8 PcdApertureSize;
UINT8 PcdGttSize;
UINT8 PcdLegacySegDecode;
int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
uint16_t gpu_pipeb_power_on_delay;
uint16_t gpu_pipeb_light_on_delay;
uint16_t gpu_pipeb_power_off_delay;
uint16_t gpu_pipeb_light_off_delay;
uint16_t gpu_pipeb_power_cycle_delay;
int gpu_pipeb_pwm_freq_hz;
int disable_ddr_2x_refresh_rate;
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during
* SiliconInit.
*/
UINT8 PcdSdcardMode;
UINT8 PcdEnableHsuart0;
UINT8 PcdEnableHsuart1;
UINT8 PcdEnableAzalia;
UINT32 AzaliaConfigPtr;
UINT8 PcdEnableSata;
UINT8 PcdEnableXhci;
UINT8 PcdEnableLpe;
UINT8 PcdEnableDma0;
UINT8 PcdEnableDma1;
UINT8 PcdEnableI2C0;
UINT8 PcdEnableI2C1;
UINT8 PcdEnableI2C2;
UINT8 PcdEnableI2C3;
UINT8 PcdEnableI2C4;
UINT8 PcdEnableI2C5;
UINT8 PcdEnableI2C6;
UINT32 PcdGraphicsConfigPtr;
UINT8 PunitPwrConfigDisable;
UINT8 ChvSvidConfig;
UINT8 DptfDisable;
UINT8 PcdEmmcMode;
UINT8 PcdUsb3ClkSsc;
UINT8 PcdDispClkSsc;
UINT8 PcdSataClkSsc;
UINT8 Usb2Port0PerPortPeTxiSet;
UINT8 Usb2Port0PerPortTxiSet;
UINT8 Usb2Port0IUsbTxEmphasisEn;
UINT8 Usb2Port0PerPortTxPeHalf;
UINT8 Usb2Port1PerPortPeTxiSet;
UINT8 Usb2Port1PerPortTxiSet;
UINT8 Usb2Port1IUsbTxEmphasisEn;
UINT8 Usb2Port1PerPortTxPeHalf;
UINT8 Usb2Port2PerPortPeTxiSet;
UINT8 Usb2Port2PerPortTxiSet;
UINT8 Usb2Port2IUsbTxEmphasisEn;
UINT8 Usb2Port2PerPortTxPeHalf;
UINT8 Usb2Port3PerPortPeTxiSet;
UINT8 Usb2Port3PerPortTxiSet;
UINT8 Usb2Port3IUsbTxEmphasisEn;
UINT8 Usb2Port3PerPortTxPeHalf;
UINT8 Usb2Port4PerPortPeTxiSet;
UINT8 Usb2Port4PerPortTxiSet;
UINT8 Usb2Port4IUsbTxEmphasisEn;
UINT8 Usb2Port4PerPortTxPeHalf;
UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
UINT8 PcdSataInterfaceSpeed;
UINT8 PcdPchUsbSsicPort;
UINT8 PcdPchUsbHsicPort;
UINT8 PcdPcieRootPortSpeed;
UINT8 PcdPchSsicEnable;
UINT32 PcdLogoPtr;
UINT32 PcdLogoSize;
UINT8 PcdRtcLock;
UINT8 PMIC_I2CBus;
UINT8 ISPEnable;
UINT8 ISPPciDevConfig;
};
extern struct chip_operations soc_intel_baytrail_ops;
#endif /* _BAYTRAIL_CHIP_H_ */
extern struct chip_operations soc_intel_braswell_ops;
#endif /* _SOC_CHIP_H_ */