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mb/google/trulo: Support OCP fault on A0/1 ports

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The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.

BUG=b:335858378
TEST= Able to build google/trulo

Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Pranava Y N 2024-05-24 14:20:14 +05:30 committed by Subrata Banik
parent 11fad8fc86
commit 3303b3684b
2 changed files with 10 additions and 3 deletions
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5
src/mainboard/google/brya/variants/trulo/gpio.c
View File

@ -8,7 +8,10 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* TODO */
/* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */
PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG),
/* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */
PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG),
};
/* Early pad configuration in bootblock */

8
src/mainboard/google/brya/variants/trulo/overridetree.cb
View File

@ -1,4 +1,8 @@
chip soc/intel/alderlake
device domain 0 on
end
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
device domain 0 on
end
end