soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
@@ -168,6 +168,11 @@ struct soc_intel_braswell_config {
|
||||
UINT8 I2C4Frequency;
|
||||
UINT8 I2C5Frequency;
|
||||
UINT8 I2C6Frequency;
|
||||
UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/
|
||||
UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/
|
||||
UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/
|
||||
UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/
|
||||
UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/
|
||||
};
|
||||
|
||||
extern struct chip_operations soc_intel_braswell_ops;
|
||||
|
Reference in New Issue
Block a user