mb/system76/gaze16: Split gpio.h into data files
Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for ramstage to match other System76 boards. Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
committed by
Martin Roth
parent
b312f196c9
commit
34c8a19f92
@@ -1,11 +1,13 @@
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
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@@ -5,5 +5,5 @@
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void bootblock_mainboard_init(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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variant_configure_early_gpios();
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}
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9
src/mainboard/system76/gaze16/include/variant/gpio.h
Normal file
9
src/mainboard/system76/gaze16/include/variant/gpio.h
Normal file
@@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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void variant_configure_early_gpios(void);
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void variant_configure_gpios(void);
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#endif
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@@ -10,5 +10,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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params->PchLegacyIoLowLatency = 1;
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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variant_configure_gpios();
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}
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@@ -1,17 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <soc/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
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};
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#include <variant/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
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};
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#endif /* VARIANT_GPIO_H */
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void variant_configure_gpios(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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}
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
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};
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void variant_configure_early_gpios(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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@@ -1,17 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <soc/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
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};
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#include <variant/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
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};
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#endif /* VARIANT_GPIO_H */
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void variant_configure_gpios(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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}
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
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};
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void variant_configure_early_gpios(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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