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mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe

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NVMe using clk_src[0] and clk_req[1] mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=0,clk_req=1 in mFIT.

BUG=b:328318578
TEST=build firmware and veirfy suspend function on NVMe SKU DUT.

Cq-Depend: chrome-internal:7063434
Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Seunghwan Kim 2024-03-14 15:15:40 +09:00 committed by Felix Held
parent 3ac72f8cf2
commit 3588243177
1 changed files with 5 additions and 2 deletions
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7
src/mainboard/google/brya/variants/xol/overridetree.cb
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@ -268,10 +268,13 @@ chip soc/intel/alderlake
end end
end end
device ref pcie4_0 on device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0 # Enable NVMe SSD using clk_src0 and clk_req1 mapping to hardware
# design. Due to inconsistency between PMC firmware and FSP, we need
# to set clk_src to clk_req number, not same as hardware mapping in
# coreboot. Then swap correct setting clksrc, clkreq in mFIT.
register "cpu_pcie_rp[CPU_RP(1)]" = "{ register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1, .clk_req = 1,
.clk_src = 0, .clk_src = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
probe STORAGE STORAGE_NVME probe STORAGE STORAGE_NVME