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soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility

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This commit updates the type definitions for FSP parameters in the
Meteor Lake platform to ensure compatibility with the FSP2.4
specification, that supports 64-bit builds for the first time and
this  also ensures that parameter types works for both 32-bit
and 64-bit builds.

- In fsp_params.c, FSPS_ARCH_UPD macro is changed to
  FSPS_ARCHx_UPD which supports FSP2.4 and older specifications.
  Special handling is added for FspEventHandler assignment to handle
  as the variable type is different in both cases.

- In meminit.c, the type for SPD pointers is changed from uint32_t
  to efi_uintn_t to support both 32-bit and 64-bit builds.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Appukuttan V K
2024-05-03 10:32:34 +05:30
committed by Subrata Banik
parent 8c3cf9eace
commit 3725fce22b
3 changed files with 15 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/meteorlake/fsp_params.c
View File

@@ -703,7 +703,7 @@ static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
}
static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg)
{
/*
* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit
@@ -713,8 +713,14 @@ static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
/* Assign FspEventHandler arch Upd to use coreboot debug event handler */
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
CONFIG(FSP_ENABLE_SERIAL_DEBUG))
#if CONFIG(PLATFORM_USES_FSP2_X86_32)
s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER)
fsp_debug_event_handler;
#else
s_arch_cfg->FspEventHandler = (EFI_PHYSICAL_ADDRESS)
fsp_debug_event_handler;
#endif
}
static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
@@ -822,7 +828,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
struct soc_intel_meteorlake_config *config;
FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;
config = config_of_soc();
arch_silicon_init_params(s_arch_cfg);

4
src/soc/intel/meteorlake/meminit.c
View File

@@ -77,7 +77,7 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
{
uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
@@ -106,7 +106,7 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
bool enable_channel = 0;
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
uint32_t *spd_ptr = spd_upds[ch][dimm];
efi_uintn_t *spd_ptr = spd_upds[ch][dimm];
*spd_ptr = data->spd[ch][dimm];
if (*spd_ptr)

10
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@@ -446,7 +446,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
#define VGA_INIT_CONTROL_TEAR_DOWN BIT(1)
static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
FSPM_ARCH_UPD *arch_upd)
FSPM_ARCHx_UPD *arch_upd)
{
void *vbt;
size_t vbt_size;
@@ -485,22 +485,22 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);
m_cfg->VgaInitControl = vga_init_control;
m_cfg->VbtPtr = (UINT32)vbt;
m_cfg->VbtPtr = (efi_uintn_t)vbt;
m_cfg->VbtSize = vbt_size;
m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
m_cfg->VgaMessage = (UINT32)text;
m_cfg->VgaMessage = (efi_uintn_t)text;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_meteorlake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
enum fsp_log_level log_level = fsp_map_console_log_level();
arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
arch_upd->FspEventHandler = (efi_uintn_t)((FSP_EVENT_HANDLER *)
fsp_debug_event_handler);
/* Set Serial debug message level */
m_cfg->PcdSerialDebugLevel = log_level;