issue 41 - fix up motherboard compilation. There's always hope.

1201_ht_bus0_dev0_fidvid_mb.diff part 1



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/Iwill/DK8S2/Options.lb

@@ -60,7 +60,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/Iwill/DK8S2/auto.c

@@ -19,7 +19,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/Iwill/DK8S2/cmos.layout

@@ -29,9 +29,10 @@ entries
 386          1       e       1        ECC_memory
 388          4       r       0        reboot_bits
 392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -39,8 +40,15 @@ entries
 424          4       e       7        boot_third
 428          4       h       0        boot_index
 432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
 444          1       e       1        nmi
-1008         16      h       0        check_sum
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
 
 enumerations
 
@@ -70,7 +78,21 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
 
 checksums
 
 checksum 392 983 984
+
+

src/mainboard/Iwill/DK8X/auto.c

@@ -19,7 +19,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 
 #include "superio/NSC/pc87360/pc87360_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"

src/mainboard/agami/aruma/Options.lb

@@ -52,6 +52,11 @@ uses CONFIG_PCI_ROM_RUN
 
 uses CONFIG_USE_INIT
 
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+
 ###
 ### Build options
 ###
@@ -112,6 +117,10 @@ default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=4
 #default ALLOW_HT_OVERCLOCKING=1
 
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
 ##
 ## Build code to setup a generic IOAPIC
 ##

src/mainboard/agami/aruma/auto.c

@@ -1,6 +1,4 @@
 #define ASSEMBLY 1
-#define ENABLE_APIC_EXT_ID 1
-#define APIC_ID_OFFSET 0x10
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -20,12 +18,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -93,6 +89,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "cpu/amd/dualcore/dualcore.c"
 #include "sdram/generic_sdram.c"
 #include "resourcemap.c"
 

src/mainboard/agami/aruma/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -42,10 +43,6 @@ entries
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu
-# These two can be used to control link speeds. byte 56
-449          1       e       1        amdk8_1GHz
-450          1       e       1        amd8131_800MHz
-#
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

src/mainboard/agami/aruma/mainboard.c

@@ -10,7 +10,7 @@
 
 #include <arch/io.h>
 #include "../../../northbridge/amd/amdk8/northbridge.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "chip.h"
 
 #include "pc80/mc146818rtc.h"

src/mainboard/amd/quartet/Options.lb

@@ -59,7 +59,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/amd/quartet/auto.c

@@ -14,7 +14,6 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -22,11 +21,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/NSC/pc87360/pc87360_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
@@ -154,6 +152,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 // #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
 #include "sdram/generic_sdram.c"
 /* quartet does not want the default */
 #include "resourcemap.c"

src/mainboard/amd/quartet/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -41,6 +42,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

src/mainboard/amd/serenade/Options.lb

@@ -58,7 +58,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/amd/serenade/auto.c

@@ -21,7 +21,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/amd/serenade/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -41,6 +42,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
@@ -76,10 +78,10 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
-8     0     200Mhz
+8     0     400Mhz
-8     1     166Mhz
+8     1     333Mhz
-8     2     133Mhz
+8     2     266Mhz
-8     3     100Mhz
+8     3     200Mhz
 9     0     off
 9     1     87.5%
 9     2     75.0%

src/mainboard/amd/serengeti_leopard/Config.lb

@@ -45,17 +45,25 @@ driver mainboard.o
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE object mptable.o end
+if HAVE_MP_TABLE 
+	object mptable.o 
+end
+
 if HAVE_PIRQ_TABLE 
 	object irq_tables.o 
 end
 
 if HAVE_ACPI_TABLES
- object acpi_tables.o
+ 	object acpi_tables.o
- object fadt.o
+	object fadt.o
- object dsdt.o
+	if K8_SB_HT_CHAIN_ON_BUS0
- object ssdt.o
+		object dsdt_bus0.o
-	if ACPI_SSDTX_NUM 
+	else
+		object dsdt.o
+	end
+	object ssdt.o
+	if ACPI_SSDTX_NUM
+		if K8_SB_HT_CHAIN_ON_BUS0
 		 object ssdt2.o
 		# object ssdt3.o
 		# object ssdt4.o
@@ -63,6 +71,15 @@ if HAVE_ACPI_TABLES
                 # object ssdt6.o
                 # object ssdt7.o
                 # object ssdt8.o
+		else
+                 object ssdt2_bus0.o
+                # object ssdt3_bus0.o
+                # object ssdt4_bus0.o
+                # object ssdt5_bus0.o
+                # object ssdt6_bus0.o
+                # object ssdt7_bus0.o
+                # object ssdt8_bus0.o
+		end
 	end
 end
 
@@ -70,61 +87,65 @@ object reset.o
 
 if USE_DCACHE_RAM
 
-if CONFIG_USE_INIT
+	if CONFIG_USE_INIT
+		# compile cache_as_ram.c to auto.o
+		makerule ./cache_as_ram_auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o" 
+		end
 
-makerule ./auto.o
+	else   
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		#compile cache_as_ram.c to auto.inc 
-        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+		makerule ./cache_as_ram_auto.inc
-end
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+		        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
 
-else    
+	end
-                
-makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
-        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
-end
-
-end
 else
   
-##
+	##
-## Romcc output
+	## Romcc output
-##
+	##
-makerule ./failover.E
+	makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
+        	depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+	end
 
-makerule ./failover.inc
+	makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
+        	depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+	end
 
-makerule ./auto.E
+	makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+	end
-makerule ./auto.inc
+	makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+	end
 
 end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
 if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
 
         if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
+                ldscript /cpu/amd/car/cache_as_ram.lds
         end
 end
 
@@ -141,8 +162,8 @@ end
 
 if USE_DCACHE_RAM
 else
-### Should this be in the northbridge code?
+	### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
+	mainboardinit arch/i386/lib/cpu_reset.inc
 end
 
 ##
@@ -152,10 +173,10 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 if USE_DCACHE_RAM
-##
+	##
-## Setup Cache-As-Ram
+	## Setup Cache-As-Ram
-##
+	##
-mainboardinit cpu/amd/car/cache_as_ram.inc
+	mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
 ###
@@ -164,12 +185,12 @@ end
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
+	if USE_DCACHE_RAM
-       ldscript /arch/i386/lib/failover.lds
+		ldscript /arch/i386/lib/failover.lds
-else
+	else
-       ldscript /arch/i386/lib/failover.lds
+       		ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
+	        mainboardinit ./failover.inc
-end
+	end
 end
 
 ###
@@ -181,23 +202,23 @@ end
 ##
 if USE_DCACHE_RAM
 
-if CONFIG_USE_INIT
+	if CONFIG_USE_INIT
-initobject auto.o
+		initobject cache_as_ram_auto.o
-else
+	else
-mainboardinit ./auto.inc
+		mainboardinit ./cache_as_ram_auto.inc
-end
+	end
 
 else
 
-##
+	##
-## Setup RAM
+	## Setup RAM
-##
+	##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
+	mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
+	mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
+	mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
+	mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
+	mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
+	mainboardinit cpu/x86/mmx/disable_mmx.inc
 
 end
 
@@ -208,7 +229,7 @@ if CONFIG_CHIP_NAME
 	config chip.h
 end
 
-# sample config for amd/serengeti_leopard 
+# sample config for amd/serengeti_cheetah 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on
                 chip cpu/amd/socket_940
@@ -237,7 +258,7 @@ chip northbridge/amd/amdk8/root_complex
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
+							device pnp 2e.0 off #  Floppy
                 	                 			io 0x60 = 0x3f0
                 	                			irq 0x70 = 6
                 	                			drq 0x74 = 2
@@ -250,7 +271,7 @@ chip northbridge/amd/amdk8/root_complex
                 	                 			io 0x60 = 0x3f8
                 	                			irq 0x70 = 4
 							end
-                	        			device pnp 2e.3 on #  Com2
+                	        			device pnp 2e.3 off #  Com2
                 	                 			io 0x60 = 0x2f8
                 	                			irq 0x70 = 3
 							end
@@ -282,19 +303,31 @@ chip northbridge/amd/amdk8/root_complex
 					device pci 1.3 on
                                                 chip drivers/i2c/i2cmux # pca9556 smbus mux
                                                         device i2c 18 on #0 pca9516 1
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 18 on #1 pca9516 2
                                                                 chip drivers/generic/generic #dimm 1-0-0
                                                                         device i2c 50 on end
                                                                 end
                                                                 chip drivers/generic/generic #dimm 1-0-1
                                                                         device i2c 51 on end
                                                                 end
-                                                        end
+                                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 18 on #1 pca9516 2
+                                                                        device i2c 52 on end
-                                                                chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
                                                                 end
-                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                chip drivers/generic/generic #dimm 1-1-1
-                                                                        device i2c 51 on end
+                                                                        device i2c 53 on end
                                                                 end
                                                         end
 						end
@@ -330,7 +363,7 @@ chip northbridge/amd/amdk8/root_complex
 
 
 	end #pci_domain
-#       chip drivers/generic/debug
+#        chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
 #                device pnp 0.1 on end # pci_regs_all
 #                device pnp 0.2 off end # mem
@@ -343,3 +376,4 @@ chip northbridge/amd/amdk8/root_complex
 
 end
 
+

src/mainboard/amd/serengeti_leopard/Options.lb

@@ -54,13 +54,29 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+
 ###
 ### Build options
 ###
@@ -73,7 +89,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -123,23 +141,51 @@ default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
+#default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x8
+default LIFT_BSP_APIC_ID=0
+
 #CHIP_NAME ?
 default CONFIG_CHIP_NAME=1
 
-#1G memory hole
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+#2G
+default K8_HW_MEM_HOLE_SIZEK=0x200000
+#1G
+#default K8_HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default K8_HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default K8_HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
+#HT Unit ID offset
+default HT_CHAIN_UNITID_BASE=0x4
+
+#real SB Unit ID
+default HT_CHAIN_END_UNITID_BASE=0x1
+
+#make the SB HT chain on bus 0
+default K8_SB_HT_CHAIN_ON_BUS0=1
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
 default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_BASE=0xcc000
-default DCACHE_RAM_SIZE=0x1000
+default DCACHE_RAM_SIZE=0x4000
 default CONFIG_USE_INIT=1
 
 ##

src/mainboard/amd/serengeti_leopard/acpi_tables.c

@@ -1,36 +1,7 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
 /*
- *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+ *
+ *  Copyright 2005 AMD
+ *  2005.9 yhlu make it more dynamic for AMD Opteron Based MB
  */
 
 #include <console/console.h>
@@ -41,7 +12,7 @@ acknowledgement of AMD's proprietary rights in them.
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 
-#define DUMP_ACPI_TABLES 1
+#define DUMP_ACPI_TABLES 0
 
 #if DUMP_ACPI_TABLES == 1
 static void dump_mem(unsigned start, unsigned end)
@@ -107,7 +78,7 @@ unsigned long acpi_fill_madt(unsigned long current)
         {
                 device_t dev;
                 struct resource *res;
-                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1,1));
+                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1 + HT_CHAIN_UNITID_BASE - 1, 1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
@@ -117,7 +88,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
                         }
                 }
-                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2,1));
+                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2 + HT_CHAIN_UNITID_BASE - 1, 1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
@@ -248,7 +219,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	
 	acpi_write_rsdp(rsdp, rsdt);
 	acpi_write_rsdt(rsdt);
-	
+
 	/*
 	 * We explicitly add these tables later on:
 	 */
@@ -265,6 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current+=madt->header.length;
 	acpi_add_table(rsdt,madt);
 
+
 	/* SRAT */
         printk_debug("ACPI:    * SRAT\n");
         srat = (acpi_srat_t *) current;

src/mainboard/amd/serengeti_leopard/auto.c

@@ -1,38 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 #define ASSEMBLY 1
  
 #include <stdint.h>
@@ -54,7 +19,7 @@ acknowledgement of AMD's proprietary rights in them.
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -182,11 +147,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
 #endif
 
+#include "cpu/amd/dualcore/dualcore.c"
+
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)

src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c

@@ -1,42 +1,28 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 #define ASSEMBLY 1
 #define __ROMCC__
- 
+
+#define RAMINIT_SYSINFO 0
+
+#if CONFIG_LOGICAL_CPUS==1
+        #define SET_NB_CFG_54 1
+#endif
+
+//use by raminit
+#define K8_4RANK_DIMM_SUPPORT 1
+
+//use bu init_cpus
+#if 0
+        #define ENABLE_APIC_EXT_ID 1
+        #define APIC_ID_OFFSET 0x10
+        #define LIFT_BSP_APIC_ID 0
+#else
+        #define ENABLE_APIC_EXT_ID 0
+#endif
+
+//used by incoherent_ht
+//#define K8_SCAN_PCI_BUS 1
+//#define K8_ALLOCATE_IO_RANGE 1
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -60,9 +46,7 @@ static void post_code(uint8_t value) {
 }
 #endif
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h> 
-#define K8_HT_FREQ_1G_SUPPORT 0
-#define K8_SCAN_PCI_BUS 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -85,34 +69,17 @@ static void post_code(uint8_t value) {
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
 static void hard_reset(void)
 {
         device_t dev;
+	unsigned sblnk = get_sblnk();
 
         /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+	dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 3);
+#else
+	dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 3);
+#endif
 
         set_bios_reset();
 
@@ -121,13 +88,17 @@ static void hard_reset(void)
         /* reset */
         outb(0x0e, 0x0cf9);
 }
-
 static void soft_reset(void)
 {
         device_t dev;
+	unsigned sblnk = get_sblnk();
 
         /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+        dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 0);
+#else
+        dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 0);
+#endif
 
         set_bios_reset();
         pci_write_config8(dev, 0x47, 1);
@@ -187,32 +158,15 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
 
 #include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else 
-        #define ENABLE_APIC_EXT_ID 0
-#endif
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
  /* tyan does not want the default */
 #include "resourcemap.c" 
 
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
 #include "cpu/amd/dualcore/dualcore.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 
 #define RC0 ((1<<0)<<8)
 #define RC1 ((1<<1)<<8)
@@ -221,45 +175,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define DIMM1 0x51
 
 #include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
 
 #if USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void real_main(unsigned long bist);
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-
-void amd64_main(unsigned long bist)
 {
-#if CONFIG_LOGICAL_CPUS==1
+        unsigned last_boot_normal_x = last_boot_normal();
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-        /* Make cerain my local apic is useable */
-//        enable_lapic();
 
-#if CONFIG_LOGICAL_CPUS==1
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        id = get_node_core_id_x();
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
-        /* Is this a cpu only reset? */
+                if (last_boot_normal_x) {
-        if (cpu_init_detected(id.nodeid)) {
-#else
-//        nodeid = lapicid();
-	nodeid = get_node_id();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-                if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto cpu_reset;
-                }
-        }
-
-        /* Is this a secondary cpu? */
-//        post_code(0x21);
-        if (!boot_cpu()) {
-                if (last_boot_normal()) {
                         goto normal_image;
                 } else {
                         goto fallback_image;
@@ -271,12 +202,12 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
+        /* Setup the flash access */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
 //        post_code(0x22);
-        if (bios_reset_detected() && last_boot_normal()) {
+        if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
         /* This is the primary cpu how should I boot? */
@@ -290,129 +221,47 @@ void amd64_main(unsigned long bist)
 //        post_code(0x23);
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
- cpu_reset:
-//        post_code(0x24);
-#if 0
-        //CPU reset will reset memtroller ???
-        asm volatile ("jmp __cpu_reset" 
-                : /* outputs */ 
-                : "a"(bist) /* inputs */
-                );
-#endif
 
  fallback_image:
 //        post_code(0x25);
-        real_main(bist);
+	;
 }
-void real_main(unsigned long bist)
-#else
-void amd64_main(unsigned long bist)
 #endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, 0, 0, 0 },
-                        .channel1 = { RC0|DIMM1, 0, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, 0 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, 0 , 0, 0 },
 
-                },
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
 #endif
+        real_main(bist, cpu_init_detectedx);
 
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+                        RC0|DIMM0, 0, 0, 0,
+                        RC0|DIMM1, 0, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                        RC1|DIMM0, 0 , 0, 0,
+                        RC1|DIMM1, 0 , 0, 0,
+#endif
 	};
 
         int needs_reset;
 	unsigned cpu_reset = 0;
+	unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
 
         if (bist == 0) {
-#if CONFIG_LOGICAL_CPUS==1
+		bsp_apicid = init_cpus(cpu_init_detectedx);
-        	struct node_core_id id;
-#else
-	        unsigned nodeid;
-#endif
-                /* Skip this if there was a built in self test failure */
-//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-		id = get_node_core_id_x(); // that is initid
-        #if ENABLE_APIC_EXT_ID == 1
-                if(id.coreid == 0) {
-                        enable_apic_ext_id(id.nodeid);
-                }
-        #endif
-#else
-                nodeid = get_node_id();
-        #if ENABLE_APIC_EXT_ID == 1
-                enable_apic_ext_id(nodeid);
-        #endif
-#endif
-
-                enable_lapic();
-                init_timer();
-
-//                post_code(0x30);
-
-#if CONFIG_LOGICAL_CPUS==1
-        #if (ENABLE_APIC_EXT_ID == 1) 
-            #if LIFT_BSP_APIC_ID == 0
-                if( id.nodeid != 0 ) //all except cores in node0
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
-        #endif
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-//                                __asm__ volatile ("jmp __cpu_reset");
-				cpu_reset = 1;
-				goto cpu_reset_x;
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-//                        start_other_core(id.nodeid);
-                }
-#else
-        #if (ENABLE_APIC_EXT_ID == 1) 
-            #if LIFT_BSP_APIC_ID == 0
-                if(nodeid != 0)
-            #endif
-                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
-
-        #endif
-                if (cpu_init_detected(nodeid)) {
-//                        __asm__ volatile ("jmp __cpu_reset");
-			cpu_reset = 1;
-			goto cpu_reset_x;
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-//                post_code(0x31);
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-			// We need stop the CACHE as RAM for this CPU too
-			#include "cpu/amd/car/cache_as_ram_post.c"
-                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
-                }
         }
 
 //	post_code(0x32);
@@ -426,6 +275,8 @@ void amd64_main(unsigned long bist)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
         setup_serengeti_leopard_resource_map();
 #if 0
         dump_pci_device(PCI_DEV(0, 0x18, 0));
@@ -436,22 +287,24 @@ void amd64_main(unsigned long bist)
 	
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+	wait_all_core0_started();
         start_other_cores();
 #endif
-#if 0
+	wait_all_aps_started(bsp_apicid);
 
-	// You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec
-        needs_reset |= ht_setup_chains(2);
-#else
-	// automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
-#endif
 
        	if (needs_reset) {
                	print_info("ht reset -\r\n");
                	soft_reset();
        	}
 
+	allow_all_aps_stop(bsp_apicid);
+
+        nodes = get_nodes();
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
+
 	enable_smbus();
 #if 0
 	dump_spd_registers(&cpu[0]);
@@ -461,7 +314,10 @@ void amd64_main(unsigned long bist)
 #endif
 
 	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+//	init_timer(); // Need to use TMICT to synconize FID/VID
+
+	sdram_initialize(nodes, ctrl);
 
 #if 0
         print_pci_devices();
@@ -471,109 +327,6 @@ void amd64_main(unsigned long bist)
 	dump_pci_devices();
 #endif
 
-        /* Check all of memory */
+	post_cache_as_ram(cpu_reset);
-#if 0
-        msr_t msr;
-        msr = rdmsr(TOP_MEM2);
-        print_debug("TOP_MEM2: ");
-        print_debug_hex32(msr.hi);
-        print_debug_hex32(msr.lo);
-        print_debug("\r\n");
-#endif
-#if 0
-        ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#endif
-
-#if 0
-        // Check 16MB of memory @ 0
-        ram_check(0x00000000, 0x00100000);
-        // Check 16MB of memory @ 2GB 
-        ram_check(0x80000000, 0x80100000);
-#endif
-
-#if 1
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-#if CONFIG_USE_INIT
-        printk_debug("v_esp=%08x\r\n", v_esp);
-#else           
-        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
-#endif    
-        }
-#endif
-
-#if 1
-
-
-cpu_reset_x:
-
-#if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
-#else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
-#endif
-
-	if(cpu_reset == 0) {
-	        print_debug("Clearing initial memory region: ");
-	}
-	print_debug("No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-	if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-	else {
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/amd/car/cache_as_ram_post.c"
-	}
-
-	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n\t"
-			:"=a" (new_cpu_reset)
-		);
-
-		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
-		if(new_cpu_reset==0) {        
-		        print_debug("done\r\n");	
-		} else 
-		{	
-			print_debug("\r\n");
-		}
-
-#if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
-#else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
-#endif
-		/*copy and execute linuxbios_ram */
-		copy_and_run(new_cpu_reset);
-		/* We will not return */
-	}
-#endif
-
-
-	print_debug("should not be here -\r\n");
 
 }

src/mainboard/amd/serengeti_leopard/dsdt.c

@@ -1,42 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-/*
- * Compilation of "dsdt_lb.dsl" - Sat Sep 17 23:29:24 2005
- *
- */
 unsigned char AmlCode[] = 
 {
     0x44,0x53,0x44,0x54,0xD7,0x18,0x00,0x00,  /* 00000000    "DSDT...." */

src/mainboard/amd/serengeti_leopard/dx/amd8111.asl

@@ -1,38 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 //AMD8111
             Name (APIC, Package (0x04)
             {

src/mainboard/amd/serengeti_leopard/dx/amd8111_isa.asl

@@ -1,38 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 //AMD8111 isa
 
             Device (ISA)

src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl

@@ -1,38 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 //AMD8111 pic LNKA B C D
 
             Device (LNKA)

src/mainboard/amd/serengeti_leopard/dx/amd8131.asl

@@ -1,39 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-//8131
 		
             Device (PG0A)
             {

src/mainboard/amd/serengeti_leopard/dx/amd8151.asl

@@ -1,39 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 // AMD8151 
             Device (AGPB)
             {

src/mainboard/amd/serengeti_leopard/dx/amdk8_util.asl

@@ -1,39 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 
 //AMD k8 util for BUSB and res range
 

src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl

@@ -1,38 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
 {
     Scope (_PR)

src/mainboard/amd/serengeti_leopard/dx/pci1_hc.asl

@@ -1,38 +1,2 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 	Include ("amd8111.asl") //real SB at first
 	Include ("amd8131.asl")

src/mainboard/amd/serengeti_leopard/dx/pci2.asl

@@ -1,38 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
 {
     Scope (_SB)

src/mainboard/amd/serengeti_leopard/dx/pci2_hc.asl

@@ -1,37 +1 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 	Include ("amd8151.asl")

src/mainboard/amd/serengeti_leopard/dx/superio.asl

@@ -1,37 +1 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 //	Include ("w83627hf.asl")

src/mainboard/amd/serengeti_leopard/fadt.c

@@ -2,42 +2,6 @@
  * ACPI - create the Fixed ACPI Description Tables (FADT)
  * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
  */
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 
 #include <string.h>
 #include <console/console.h>

src/mainboard/amd/serengeti_leopard/failover.c

@@ -1,39 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 #define ASSEMBLY 1
 #include <stdint.h>
 #include <device/pci_def.h>

src/mainboard/amd/serengeti_leopard/get_bus_conf.c

@@ -1,39 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -77,7 +41,11 @@ unsigned sbdn;
 static unsigned get_sbdn(void)
 {
         device_t dev;
-        unsigned sbdn = 3;// 8111 unit id base is 3 if 8131 before it
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+        unsigned sbdn = 1 + HT_CHAIN_END_UNITID_BASE -1;
+#else
+        unsigned sbdn = 3 + HT_CHAIN_UNITID_BASE - 1; // 8111 unit id base is 3 if 8131 before it
+#endif
         dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI , 0); //FIXME: if 8111 PCI is disabled?
         if(dev)  {
                 sbdn = (dev->path.u.pci.devfn >> 3) & 0x1f;
@@ -115,25 +83,32 @@ void get_bus_conf(void)
         dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
         if (dev) {
                 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
                 bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 bus_isa++;
 //		printk_debug("bus_isa=%d\n",bus_isa);
+#endif
         }
 	else {
                 printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
         }
 
         /* 8132-1 */
-        dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x01,0));
+        dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x01 + HT_CHAIN_UNITID_BASE - 1,0));
         if (dev) {
                 bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+                bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                bus_isa++;
+//              printk_debug("bus_isa=%d\n",bus_isa);
+#endif
         }
         else {
                 printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8132_0);
         }
 
         /* 8132-2 */
-        dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x02,0));
+        dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x02 + HT_CHAIN_UNITID_BASE - 1,0));
         if (dev) {
                 bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
@@ -146,7 +121,12 @@ void get_bus_conf(void)
 //                bus_8151_0 = node_link_to_bus( (pci1234[1]>>4) & 0xf, (pci1234[1]>>8) & 0xf);
 		bus_8151_0 = (pci1234[1] >> 16) & 0xff;
                 /* 8151 */
-        	dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02,0));
+#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+		dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02, 0)); // FIXME : still use 1 for one device ? or do that for SB chain?
+#else
+        	dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02 + HT_CHAIN_UNITID_BASE - 1,0)); // FIXME : still use 1 for one device ? or do that for SB chain?
+#endif
+
               	if (dev) {
                        	bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 //                        printk_debug("bus_8151_1=%d\n",bus_8151_1);

src/mainboard/amd/serengeti_leopard/irq_tables.c

@@ -1,39 +1,9 @@
-/*============================================================================
+/* This file was generated by getpir.c, do not modify! 
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+   (but if you do, please run checkpir on it to verify)
-This software and any related documentation (the "Materials") are the
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
 
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
 #include <console/console.h>
 #include <device/pci.h>
 #include <string.h>
@@ -120,7 +90,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq->version  = PIRQ_VERSION;
 	
 	pirq->rtr_bus = bus_8111_0;
-	pirq->rtr_devfn = (4<<3)|0;
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+	pirq->rtr_devfn = ((2+HT_CHAIN_END_UNITID_BASE-1)<<3)|0;
+#else
+	pirq->rtr_devfn = ((4+HT_CHAIN_UNITID_BASE-1)<<3)|0;
+#endif
 
 	pirq->exclusive_irqs = 0;
 	
@@ -136,13 +110,21 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info = (void *) ( &pirq->checksum + 1);
 	slot_num = 0;
 //pci bridge
-	write_pirq_info(pirq_info, bus_8111_0, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+	write_pirq_info(pirq_info, bus_8111_0, ((2+HT_CHAIN_END_UNITID_BASE-1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+#else
+	write_pirq_info(pirq_info, bus_8111_0, ((4+HT_CHAIN_UNITID_BASE-1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+#endif
 	pirq_info++; slot_num++;
 //pcix bridge
 //        write_pirq_info(pirq_info, bus_8132_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
 //agp bridge
-        write_pirq_info(pirq_info, bus_8151_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+        write_pirq_info(pirq_info, bus_8151_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // FIXE: Only do that on SB chain?
+#else
+	write_pirq_info(pirq_info, bus_8151_0, ((1+HT_CHAIN_UNITID_BASE-1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // FIXE: Only do that on SB chain
+#endif
         pirq_info++; slot_num++;
              
 	pirq->size = 32 + 16 * slot_num; 

src/mainboard/amd/serengeti_leopard/mainboard.c

@@ -1,39 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>

src/mainboard/amd/serengeti_leopard/mptable.c

@@ -1,39 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 #include <console/console.h>
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
@@ -99,14 +63,14 @@ void *smp_write_config_table(void *v)
         {
                 device_t dev;
 		struct resource *res;
-                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1,1));
+                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1 + HT_CHAIN_UNITID_BASE - 1, 1));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {
 				smp_write_ioapic(mc, apicid_8132_1, 0x11, res->base);
 			}
                 }
-                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2,1));
+                dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2 + HT_CHAIN_UNITID_BASE - 1, 1));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
 			if (res) {
@@ -131,7 +95,11 @@ void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_8111, 0xe);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_8111, 0xf);
 //??? What
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (4<<2)|3, apicid_8111, 0x13);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((2+HT_CHAIN_END_UNITID_BASE-1)<<2)|3, apicid_8111, 0x13);
+#else
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((4+HT_CHAIN_UNITID_BASE-1)<<2)|3, apicid_8111, 0x13);
+#endif
 // Onboard AMD USB
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
 

src/mainboard/amd/serengeti_leopard/readme_acpi.txt

@@ -1,41 +1,3 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
-
-
 At this time, For acpi support We got
 1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
 2. support MADT ---- dynamically (LinuxBIOS run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_leopard/acpi_tables.c)

src/mainboard/amd/serengeti_leopard/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_serengeti_leopard_resource_map(void)
 		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
+		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -154,7 +154,7 @@ static void setup_serengeti_leopard_resource_map(void)
 		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -181,7 +181,7 @@ static void setup_serengeti_leopard_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
+		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -211,7 +211,7 @@ static void setup_serengeti_leopard_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n 
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
 		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -252,8 +252,8 @@ static void setup_serengeti_leopard_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};

src/mainboard/amd/serengeti_leopard/ssdt.c

@@ -1,42 +1,5 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 /*
  * 
- * Compilation of "ssdt_lb_x.dsl" - Sat Sep 17 21:31:39 2005
  *
  */
 unsigned char AmlCode_ssdt[] = 

src/mainboard/amd/serengeti_leopard/ssdt2.c

@@ -1,42 +1,5 @@
-/*============================================================================
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-This software and any related documentation (the "Materials") are the
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 /*
  * 
- * Compilation of "pci2.asl" - Sat Sep 17 23:31:28 2005
  *
  */
 unsigned char AmlCode_ssdt2[] = 

src/mainboard/amd/serengeti_leopard/ssdt_lb_x.dsl

@@ -1,39 +1,6 @@
-/*============================================================================
+/*
-Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * Copyright 2005 AMD
-This software and any related documentation (the "Materials") are the
+ */
-confidential proprietary information of AMD. Unless otherwise provided in a
-software agreement specifically licensing the Materials, the Materials are
-provided in confidence and may not be distributed, modified, or reproduced in
-whole or in part by any means.
-LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
-EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
-WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
-PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
-USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
-DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
-BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
-INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
-OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
-LIMITATION MAY NOT APPLY TO YOU.
-AMD does not assume any responsibility for any errors which may appear in the
-Materials nor any responsibility to support or update the Materials. AMD
-retains the right to modify the Materials at any time, without notice, and is
-not obligated to provide such modified Materials to you.
-NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
-further information, software, technical information, know-how, or show-how
-available to you.
-U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
-RIGHTS." Use, duplication, or disclosure by the Government is subject to the
-restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
-its successor. Use of the Materials by the Government constitutes
-acknowledgement of AMD's proprietary rights in them.
-============================================================================*/
-// 2005.9 serengeti support
-// by yhlu
-//
-//=
-
 DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
 {
     /*

src/mainboard/amd/solo/Options.lb

@@ -60,7 +60,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/amd/solo/auto.c

@@ -11,7 +11,6 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -19,11 +18,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/NSC/pc87360/pc87360_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
@@ -91,6 +89,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "cpu/amd/dualcore/dualcore.c"
 #include "sdram/generic_sdram.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 

src/mainboard/amd/solo/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -41,6 +42,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

src/mainboard/arima/hdama/Options.lb

@@ -70,7 +70,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/arima/hdama/auto.c

@@ -11,7 +11,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -29,24 +29,6 @@
 /* Look up a which bus a given node/link combination is on.
  * return 0 when we can't find the answer.
  */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-	unsigned reg;
-
-	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-		unsigned config_map;
-		config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-		if ((config_map & 3) != 3) {
-			continue;
-		}
-		if ((((config_map >> 4) & 7) == node) &&
-			(((config_map >> 8) & 3) == link)) 
-		{
-			return (config_map >> 16) & 0xff;
-		}
-	}
-	return 0;
-}
 
 static void hard_reset(void)
 {

src/mainboard/ibm/e325/Options.lb

@@ -59,7 +59,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/ibm/e325/auto.c

@@ -21,7 +21,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/NSC/pc87366/pc87366_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/ibm/e325/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -41,6 +42,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
@@ -76,10 +78,10 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
-8     0     200Mhz
+8     0     400Mhz
-8     1     166Mhz
+8     1     333Mhz
-8     2     133Mhz
+8     2     266Mhz
-8     3     100Mhz
+8     3     200Mhz
 9     0     off
 9     1     87.5%
 9     2     75.0%

src/mainboard/ibm/e326/Options.lb

@@ -61,7 +61,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/ibm/e326/auto.c

@@ -21,7 +21,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/NSC/pc87366/pc87366_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/ibm/e326/cmos.layout

@@ -32,6 +32,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -41,6 +42,7 @@ entries
 432	     8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
+445          1       e       1        iommu
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
@@ -76,10 +78,10 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
-8     0     200Mhz
+8     0     400Mhz
-8     1     166Mhz
+8     1     333Mhz
-8     2     133Mhz
+8     2     266Mhz
-8     3     100Mhz
+8     3     200Mhz
 9     0     off
 9     1     87.5%
 9     2     75.0%

src/mainboard/newisys/khepri/Options.lb

@@ -58,7 +58,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot

src/mainboard/newisys/khepri/auto.c

@@ -19,7 +19,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/NSC/pc87360/pc87360_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2850/Options.lb

@@ -52,7 +52,7 @@ uses OBJCOPY
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -71,7 +71,9 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
@@ -120,7 +122,7 @@ default CONFIG_LOGICAL_CPUS=1
 default CONFIG_CHIP_NAME=1
 
 #1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1

src/mainboard/tyan/s2850/auto.c

@@ -19,7 +19,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2850/cache_as_ram_auto.c

@@ -13,7 +13,18 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#if 0
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -134,9 +145,11 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 
         enumerate_ht_chain();
 
+        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
+//        post_code(0x22);
         if (bios_reset_detected() && last_boot_normal_x) {
                 goto normal_image;
         }
@@ -148,12 +161,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                 goto fallback_image;
         }
  normal_image:
+//        post_code(0x23);
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
 
  fallback_image:
+//        post_code(0x25);
 	;
 }
 #endif
@@ -191,6 +206,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_cpus(cpu_init_detectedx);
         }
 
+//	post_code(0x32);
 	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
@@ -200,10 +216,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	report_bist_failure(bist);
 
         setup_default_resource_map();
-#if 0
-        dump_pci_device(PCI_DEV(0, 0x18, 0));
-	dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
 
 	needs_reset = setup_coherent_ht_domain();
 	
@@ -211,7 +223,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
-        // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {

src/mainboard/tyan/s2875/auto.c

@@ -20,7 +20,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2875/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2880/Config.lb

@@ -208,11 +208,11 @@ chip northbridge/amd/amdk8/root_complex
                                                         device pci 9.0 on end #broadcom
 							device pci 9.1 on end 
                                                 end
-                                                chip drivers/lsi/53c1030
+#                                                chip drivers/lsi/53c1030
-                                                        device pci a.0 on end
+#                                                        device pci a.0 on end
-                                                        device pci a.1 on end
+#                                                        device pci a.1 on end
-                                                        register "fw_address" = "0xfff8c000"
+#                                                        register "fw_address" = "0xfff8c000"
-                                                end
+#                                                end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end

src/mainboard/tyan/s2880/auto.c

@@ -20,7 +20,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2880/cache_as_ram_auto.c

@@ -14,7 +14,7 @@
 #include "ram/ramtest.c"
 
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2881/auto.c

@@ -20,7 +20,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2881/cache_as_ram_auto.c

@@ -19,7 +19,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2882/auto.c

@@ -20,7 +20,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2882/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2882/irq_tables.c

@@ -1,48 +1,303 @@
-#include <arch/pirq_routing.h>
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
 #include <device/pci.h>
-
+#include <string.h>
-#define IRQ_ROUTER_BUS		1
+#include <stdint.h>
-#define IRQ_ROUTER_DEVFN	PCI_DEVFN(4,3)
+#include <arch/pirq_routing.h>
-#define IRQ_ROUTER_VENDOR	0x1022
-#define IRQ_ROUTER_DEVICE	0x746b
-
-#define AVAILABLE_IRQS 0xdef8
-#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
-	{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
-	{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
-
-/*  Each IRQ_SLOT entry consists of:
- *  bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  
- */
 
 const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
+        PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,           /* u16 version   */
+        PIRQ_VERSION,   /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
+        32+16*15,        /* there can be total 15 devices on the bus */
-	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
+        1,           /* Where the interrupt router lies (bus) */
-	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
+        (4<<3)|3,           /* Where the interrupt router lies (dev) */
-	0x00,			/* IRQs devoted exclusively to PCI usage */
+        0,         /* IRQs devoted exclusively to PCI usage */
-	IRQ_ROUTER_VENDOR,	/* Vendor */
+        0x1022,         /* Vendor */
-	IRQ_ROUTER_DEVICE,	/* Device */
+        0x746b,         /* Device */
-	0x00,			/* Crap (miniport) */
+        0,         /* Crap (miniport) */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xb0,           /*  u8 checksum , mod 256 checksum must give zero */
+        0xff,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu
-	{	/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
+re (including checksum) */
-		/* PCI Slot 1-6 */
+        {
-		IRQ_SLOT(1, 3,1,0, 2,3,4,1 ),
+                {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		IRQ_SLOT(2, 3,2,0, 3,4,1,2 ),
+                {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
-		IRQ_SLOT(3, 2,1,0, 2,3,4,1 ),
+                {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		IRQ_SLOT(4, 2,2,0, 3,4,1,2 ),
+                {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
-		IRQ_SLOT(5, 4,5,0, 2,3,4,1 ),
+                {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
-		IRQ_SLOT(6, 4,4,0, 1,2,3,4 ),
+                {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
-		/* Onboard NICs */
+                {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
-		IRQ_SLOT(0, 2,3,0, 4,0,0,0 ),
+                {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
-		IRQ_SLOT(0, 2,4,0, 4,0,0,0 ),
+                {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		/* Let Linux know about bus 1 */
+                {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-		IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
+                {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
-	}
+                {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0},
+                {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
+                {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
+                {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
+        }
 };
+
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        device_t dev;
+        unsigned reg;
+
+        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+        if (!dev) {
+                return 0;
+        }
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                uint32_t config_map;
+                unsigned dst_node;
+                unsigned dst_link;
+                unsigned bus_base;
+                config_map = pci_read_config32(dev, reg);
+                if ((config_map & 3) != 3) {
+                        continue;
+                }
+                dst_node = (config_map >> 4) & 7;
+                dst_link = (config_map >> 8) & 3;
+                bus_base = (config_map >> 16) & 0xff;
+#if 0                           
+                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                        dst_node, dst_link, bus_base,
+                        reg, config_map);
+#endif
+                if ((dst_node == node) && (dst_link == link))
+                {
+                        return bus_base;
+                }
+        }
+        return 0;
+}
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-        return copy_pirq_routing_table(addr);
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+
+        uint8_t sum=0;
+        int i;
+
+        unsigned char bus_chain_0;
+        unsigned char bus_8131_1;
+        unsigned char bus_8131_2;
+        unsigned char bus_8111_1;
+        {
+                device_t dev;
+
+                /* HT chain 0 */
+                bus_chain_0 = node_link_to_bus(0, 0);
+                if (bus_chain_0 == 0) {
+                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        bus_chain_0 = 1;
+                }
+
+                /* 8111 */
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
+                if (dev) {
+                        bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+
+                        bus_8111_1 = 4;
+                }
+                /* 8131-1 */
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
+                if (dev) {
+                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+
+                        bus_8131_1 = 2;
+                }
+                /* 8131-2 */
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
+                if (dev) {
+                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+
+                        bus_8131_2 = 3;
+                }
+        }
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = bus_chain_0;
+	pirq->rtr_devfn = (4<<3)|3;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x1022;
+	pirq->rtr_device = 0x746b;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+
+        {
+                device_t dev;
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3));
+                if (dev) {
+                        /* initialize PCI interupts - these assignments depend
+                        on the PCB routing of PINTA-D 
+
+                        PINTA = IRQ5
+                        PINTB = IRQ9
+                        PINTC = IRQ11
+                        PINTD = IRQ10
+                        */
+                        pci_write_config16(dev, 0x56, 0xab95);
+                }
+        }
+
+        printk_debug("setting Onboard AMD Southbridge \n");
+        static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
+        write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+	
+        printk_debug("setting Onboard AMD USB \n");
+        static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
+        pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
+        write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Onboard ATI Display Adapter\n");
+        static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
+        write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Slot 1\n");
+        static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
+        write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Slot 2\n");
+        static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
+        pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
+        write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Slot 3\n");
+        static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
+        pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
+        write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Slot 4\n");
+        static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
+        pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
+        write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Slot 5 \n");
+        static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
+        pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
+        write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Onboard SI Serail ATA\n");
+        static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
+        write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Onboard Intel NIC\n");
+        static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
+        pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
+        write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
+        printk_debug("setting Onboard Adaptec  SCSI\n");
+        static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
+        pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
+        write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+#if 0
+	//??
+        write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+#endif
+
+        printk_debug("setting Onboard Broadcom NIC\n");
+        static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
+        pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
+        write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+#if 0
+	//?? what's this?
+        write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0);
+	pirq_info++; slot_num++;
+#endif
+
+#if 0	
+	//?? what's this?
+        write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0);
+	pirq_info++; slot_num++;
+#endif
+                
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
 }

src/mainboard/tyan/s2885/auto.c

@@ -19,7 +19,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s2885/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2891/auto.c

@@ -12,7 +12,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #define K8_HT_FREQ_1G_SUPPORT 0
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

src/mainboard/tyan/s2891/cache_as_ram_auto.c

@@ -21,7 +21,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2891/irq_tables.c

@@ -4,7 +4,10 @@
 
    Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
 */
-
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
 #include <arch/pirq_routing.h>
 
 const struct irq_routing_table intel_irq_routing_table = {
@@ -19,15 +22,15 @@ const struct irq_routing_table intel_irq_routing_table = {
 	0,         /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 #if CK804_DEVN_BASE==0
-	0x5a,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0x31,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 #else
-	0x4a,
+	0x19,
 #endif
 	{
 		{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		{0x5,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
+		{0x4,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		{0x5,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
+		{0x7,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
-		{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
+		{0x8,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
 		{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
 		{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
 		{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
@@ -37,7 +40,295 @@ const struct irq_routing_table intel_irq_routing_table = {
 		{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
 	}
 };
+
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        device_t dev;
+        unsigned reg;
+
+        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+        if (!dev) {
+                return 0;
+        }
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                uint32_t config_map;
+                unsigned dst_node;
+                unsigned dst_link;
+                unsigned bus_base;
+                config_map = pci_read_config32(dev, reg);
+                if ((config_map & 3) != 3) {
+                        continue;
+                }
+                dst_node = (config_map >> 4) & 7;
+                dst_link = (config_map >> 8) & 3;
+                bus_base = (config_map >> 16) & 0xff;
+#if 0                           
+                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                        dst_node, dst_link, bus_base,
+                        reg, config_map);
+#endif
+                if ((dst_node == node) && (dst_link == link))
+                {
+                        return bus_base;
+                }
+        }
+        return 0;
+}
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-        return copy_pirq_routing_table(addr);
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+
+        uint8_t sum=0;
+        int i;
+
+        unsigned char bus_ck804_0; //1
+        unsigned char bus_ck804_1; //2
+        unsigned char bus_ck804_2; //3
+        unsigned char bus_ck804_3; //4
+        unsigned char bus_ck804_4; //5
+        unsigned char bus_ck804_5; //6
+        unsigned char bus_8131_0;  //7
+        unsigned char bus_8131_1;  //8
+        unsigned char bus_8131_2;  //9 
+
+      {
+                device_t dev;
+                
+
+                bus_ck804_0 = node_link_to_bus(0, 0);
+                if (bus_ck804_0 == 0) {
+                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        bus_ck804_0 = 1;
+                }       
+                /* CK804 */
+                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
+                if (dev) {
+                        bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if 0                   
+                        bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_ck804_2++;
+#else 
+                        bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_ck804_4++;
+#endif                  
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
+
+                        bus_ck804_1 = 2;
+#if 0
+                        bus_ck804_2 = 3;
+#else
+                        bus_ck804_4 = 3;
+#endif
+
+                }
+#if 0                
+                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
+                if (dev) {
+                        bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_ck804_3++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
+
+                        bus_ck804_3 = bus_ck804_2+1;
+                }
+
+                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
+                if (dev) {
+                        bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_ck804_4++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
+
+                        bus_ck804_4 = bus_ck804_3+1;
+                }
+#endif
+
+                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
+                if (dev) {
+                        bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_ck804_5++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
+
+                        bus_ck804_5 = bus_ck804_4+1;
+                }
+
+                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
+                if (dev) {
+                        bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_8131_0++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
+
+                        bus_8131_0 = bus_ck804_5+1;
+                }
+
+		bus_8131_0 = node_link_to_bus(0, 2);
+
+                /* 8131-1 */
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
+                if (dev) {
+                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_8131_2++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+
+                        bus_8131_1 = bus_8131_0+1;
+                        bus_8131_2 = bus_8131_0+2;
+                }
+                /* 8131-2 */
+                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
+                if (dev) {
+                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+
+                        bus_8131_2 = bus_8131_1+1;
+                }
+
+
+        }
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = bus_ck804_0;
+	pirq->rtr_devfn = ((CK804_DEVN_BASE+9)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x005c;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+//pcix bridge
+        write_pirq_info(pirq_info, bus_8131_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+        pirq_info++; slot_num++;
+             
+#if 0
+//smbus
+	write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+
+//usb
+	write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+
+//audio
+	write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+//sata
+	write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+//sata
+        write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+//nic
+        write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+
+//Slot1 PCIE x16
+        write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
+        pirq_info++; slot_num++;
+
+//firewire
+        write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+
+//Slot2 pci
+        write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
+        pirq_info++; slot_num++;
+//nic   
+        write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+//Slot3 PCIE x16 
+        write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
+        pirq_info++; slot_num++;
+
+//Slot4 PCIX
+        write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
+        pirq_info++; slot_num++;
+
+//Slot5 PCIX
+        write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
+        pirq_info++; slot_num++;
+
+//onboard scsi
+        write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
+        pirq_info++; slot_num++;
+
+//Slot6 PCIX
+        write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
+        pirq_info++; slot_num++;
+#endif
+                
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
 }

src/mainboard/tyan/s2892/auto.c

@@ -12,7 +12,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #define K8_HT_FREQ_1G_SUPPORT 1
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

src/mainboard/tyan/s2892/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s2895/auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 //#define K8_HT_FREQ_1G_SUPPORT 1
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/model_fxx/model_fxx_msr.h"
+#include <cpu/amd/model_fxx_msr.h>
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"

src/mainboard/tyan/s2895/cache_as_ram_auto.c

@@ -25,7 +25,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s4880/Config.lb

@@ -208,11 +208,11 @@ chip northbridge/amd/amdk8/root_complex
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
                                         device pci 0.0 on
-                                                chip drivers/lsi/53c1030
+#                                                chip drivers/lsi/53c1030
-                                                        device pci 4.0 on end
+#                                                        device pci 4.0 on end
-                                                        device pci 4.1 on end
+#                                                        device pci 4.1 on end
-                                                        register "fw_address" = "0xfff8c000"
+#                                                        register "fw_address" = "0xfff8c000"
-                                                end
+#                                                end
                                                 chip drivers/pci/onboard
                                                         device pci 9.0 on end
                                                         device pci 9.1 on end

src/mainboard/tyan/s4880/auto.c

@@ -20,7 +20,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s4880/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s4882/auto.c

@@ -19,7 +19,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s4882/cache_as_ram_auto.c

@@ -13,7 +13,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#include "northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/tyan/s4882/mptable.c

@@ -7,6 +7,41 @@
 #include <cpu/amd/dualcore.h>
 #endif
 
+
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        device_t dev;
+        unsigned reg;
+
+        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+        if (!dev) {
+                return 0;
+        }
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                uint32_t config_map;
+                unsigned dst_node;
+                unsigned dst_link;
+                unsigned bus_base;
+                config_map = pci_read_config32(dev, reg);
+                if ((config_map & 3) != 3) {
+                        continue;
+                }
+                dst_node = (config_map >> 4) & 7;
+                dst_link = (config_map >> 8) & 3;
+                bus_base = (config_map >> 16) & 0xff;
+#if 0                           
+                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                        dst_node, dst_link, bus_base,
+                        reg, config_map);
+#endif
+                if ((dst_node == node) && (dst_link == link))
+                {
+                        return bus_base;
+                }
+        }
+        return 0;
+}
+
 void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
@@ -16,6 +51,7 @@ void *smp_write_config_table(void *v)
 
         unsigned char bus_num;
         unsigned char bus_isa;
+	unsigned char bus_chain_0;
         unsigned char bus_8131_1;
         unsigned char bus_8131_2;
         unsigned char bus_8111_1;
@@ -46,9 +82,16 @@ void *smp_write_config_table(void *v)
        
         {
                 device_t dev;
-                
+               
+                /* HT chain 0 */
+                bus_chain_0 = node_link_to_bus(0, 1);
+                if (bus_chain_0 == 0) {
+                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        bus_chain_0 = 1;
+                }
+ 
                 /* 8111 */
-                dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
                 if (dev) {
                         bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
@@ -61,7 +104,7 @@ void *smp_write_config_table(void *v)
                         bus_isa = 5;
                 }
                 /* 8131-1 */
-                dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
                 if (dev) {
                         bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
@@ -72,7 +115,7 @@ void *smp_write_config_table(void *v)
                         bus_8131_1 = 2;
                 }
                 /* 8131-2 */
-                dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
                 if (dev) {
                         bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
@@ -105,14 +148,14 @@ void *smp_write_config_table(void *v)
         {
                 device_t dev;
                 struct resource *res;
-                dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
                                 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
                         }
                 }
-                dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
+                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
@@ -141,7 +184,7 @@ void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
 	
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
 
 
 //On Board AMD USB