mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2

Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.

Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>

src/mainboard/siemens/fa_ehl/Kconfig

@@ -0,0 +1,31 @@
+config BOARD_SIEMENS_BASEBOARD_FA_EHL
+	def_bool n
+	select SOC_INTEL_ELKHARTLAKE
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_GENERIC
+	select HAVE_ACPI_TABLES
+	select DRIVER_SIEMENS_NC_FPGA
+	select NC_FPGA_NOTIFY_CB_READY
+	select USE_SIEMENS_HWILIB
+	select SOC_INTEL_DISABLE_POWER_LIMITS
+
+source "src/mainboard/siemens/fa_ehl/variants/*/Kconfig"
+
+if BOARD_SIEMENS_BASEBOARD_FA_EHL
+
+config MAINBOARD_DIR
+	default "siemens/fa_ehl"
+
+config VARIANT_DIR
+	default "fa_ehl" if BOARD_SIEMENS_FA_EHL
+
+config MAINBOARD_PART_NUMBER
+	default "FA EHL" if BOARD_SIEMENS_FA_EHL
+
+config DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
+	default y
+
+endif # BOARD_SIEMENS_BASEBOARD_FA_EHL

src/mainboard/siemens/fa_ehl/Kconfig.name

@@ -0,0 +1,5 @@
+comment "FA EHL"
+
+config BOARD_SIEMENS_FA_EHL
+	bool "-> FA EHL"
+	select BOARD_SIEMENS_BASEBOARD_FA_EHL

src/mainboard/siemens/fa_ehl/Makefile.inc

@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage_fsp_params.c
+
+ramstage-y += mainboard.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)

src/mainboard/siemens/fa_ehl/board_info.txt

@@ -0,0 +1,5 @@
+Vendor name: Siemens
+Board name: FA EHL
+Category: misc
+ROM protocol: SPI
+ROM socketed: n

src/mainboard/siemens/fa_ehl/bootblock.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}

src/mainboard/siemens/fa_ehl/dsdt.asl

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/elkhartlake/acpi/southbridge.asl>
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}

src/mainboard/siemens/fa_ehl/fa_ehl.fmd

@@ -0,0 +1,11 @@
+FLASH @0xff000000 CONFIG_ROM_SIZE {
+	SI_ALL 0x400000 {
+		SI_DESC 0x1000
+		SI_ME 0x3ff000
+	}
+	SI_BIOS 0xc00000 {
+		FMAP 0x200
+		RW_MRC_CACHE 0x10000
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/siemens/fa_ehl/mainboard.c

@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <hwilib.h>
+#include <i210.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>
+#include <string.h>
+#include <timer.h>
+#include <timestamp.h>
+
+#define MAX_PATH_DEPTH		12
+#define MAX_NUM_MAPPINGS	10
+
+/** \brief This function can decide if a given MAC address is valid or not.
+ *         Currently, addresses filled with 0xff or 0x00 are not valid.
+ * @param  mac  Buffer to the MAC address to check
+ * @return 0    if address is not valid, otherwise 1
+ */
+static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN])
+{
+	for (size_t i = 0; i < MAC_ADDR_LEN; i++) {
+		if (mac[i] != 0x00 && mac[i] != 0xff)
+			return 1;
+		if (mac[i] != mac[0])
+			return 1;
+	}
+	return 0;
+}
+
+/** \brief This function will search for a MAC address which can be assigned
+ *         to a MACPHY.
+ * @param  dev     pointer to PCI device
+ * @param  mac     buffer where to store the MAC address
+ * @return cb_err  CB_ERR or CB_SUCCESS
+ */
+enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN])
+{
+	struct bus *parent = dev->bus;
+	uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
+
+	memset(buf, 0, sizeof(buf));
+	memset(mapping, 0, sizeof(mapping));
+
+	/* The first entry in the tree is the device itself. */
+	buf[0] = dev->path.pci.devfn;
+	chain_len = 1;
+	for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
+		buf[i] = parent->dev->path.pci.devfn;
+		chain_len++;
+		parent = parent->dev->bus;
+	}
+	if (i == MAX_PATH_DEPTH) {
+		/* The path is deeper than MAX_PATH_DEPTH devices, error. */
+		printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev));
+		return CB_ERR;
+	}
+	/*
+	 * Now construct the mapping based on the device chain starting from
+	 * root bridge device to the device itself.
+	 */
+	mapping[0] = 1;
+	mapping[1] = chain_len;
+	for (i = 0; i < chain_len; i++)
+		mapping[i + 4] = buf[chain_len - i - 1];
+
+	/* Open main hwinfo block */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return CB_ERR;
+	/* Now try to find a valid MAC address in hwinfo for this mapping. */
+	for (i = 0; i < MAX_NUM_MAPPINGS; i++) {
+		if (hwilib_get_field(XMac1Mapping + i, buf, 16) != 16)
+			continue;
+		if (memcmp(buf, mapping, chain_len + 4))
+			continue;
+		/* There is a matching mapping available, get MAC address. */
+		if (hwilib_get_field(XMac1 + i, mac, MAC_ADDR_LEN) == MAC_ADDR_LEN) {
+			if (is_mac_adr_valid(mac))
+				return CB_SUCCESS;
+		}
+		return CB_ERR;
+	}
+	/* No MAC address found for */
+	return CB_ERR;
+}
+
+static void wait_for_legacy_dev(void *unused)
+{
+	uint32_t legacy_delay, us_since_boot;
+	struct stopwatch sw;
+
+	/* Open main hwinfo block. */
+	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+		return;
+
+	/* Get legacy delay parameter from hwinfo. */
+	if (hwilib_get_field(LegacyDelay, (uint8_t *)&legacy_delay,
+			      sizeof(legacy_delay)) != sizeof(legacy_delay))
+		return;
+
+	us_since_boot = get_us_since_boot();
+	/* No need to wait if the time since boot is already long enough.*/
+	if (us_since_boot > legacy_delay)
+		return;
+	stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
+	printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
+			legacy_delay - us_since_boot, legacy_delay);
+	stopwatch_wait_until_expired(&sw);
+	printk(BIOS_NOTICE, "done!\n");
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Disable CPU power states (C-states) */
+	params->Cx = 0;
+
+	/* Set maximum package C-state to PkgC0C1 */
+	params->PkgCStateLimit = 0;
+
+	/* Disable P-States */
+	params->MaxRatio = 0;
+
+	/* Disable PMC low power modes */
+	params->PmcLpmS0ixSubStateEnableMask = 0;
+	params->PmcV1p05PhyExtFetControlEn = 0;
+	params->PmcV1p05IsExtFetControlEn = 0;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
+
+static void mainboard_final(void *chip_info)
+{
+	struct device *dev;
+
+	/* Do board specific things */
+	variant_mainboard_final();
+
+	if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
+		/* Set Master Enable for on-board PCI devices if allowed. */
+		dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
+		if (dev)
+			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+		dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
+		if (dev)
+			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+	}
+}
+
+/* The following function performs board specific things. */
+void __weak variant_mainboard_final(void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	.init  = mainboard_init,
+	.final = mainboard_final
+};
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);

src/mainboard/siemens/fa_ehl/romstage_fsp_params.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/dram/common.h>
+#include <device/mmio.h>
+#include <hwilib.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	static struct spd_info spd_info;
+	const struct mb_cfg *board_cfg = variant_memcfg_config();
+	static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE];
+	const char *cbfs_hwi_name = "hwinfo.hex";
+
+	/* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to
+	   spd.bin in the case where the SPD data in HW-Info is not available or invalid. */
+	memset(spd_data, 0, sizeof(spd_data));
+	if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
+	    (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
+	    (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
+		spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
+		spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
+		spd_info.read_type = READ_SPD_MEMPTR;
+	} else {
+		die("SPD in HW-Info not valid!\n");
+	}
+	/* Initialize variant specific configurations */
+	memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false);
+
+	/* Enable Row-Hammer prevention */
+	memupd->FspmConfig.RhPrevention = 1;
+}

src/mainboard/siemens/fa_ehl/variants/baseboard/include/baseboard/variants.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+
+/* The following 2 functions return the gpio table and fill in the number
+ * of entries for each table. */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+/* This function returns SPD related FSP-M mainboard configs */
+const struct mb_cfg *variant_memcfg_config(void);
+
+/* The following function performs board specific things. */
+void variant_mainboard_final(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */

src/mainboard/siemens/fa_ehl/variants/fa_ehl/Kconfig

@@ -0,0 +1,22 @@
+if BOARD_SIEMENS_FA_EHL
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVERS_I2C_RV3028C7
+	select DRIVER_INTEL_I210
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	select EHL_TSN_DRIVER
+	select DRIVERS_ETH_PHY_M88E1512
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/fa_ehl.fmd"
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+endif # BOARD_SIEMENS_FA_EHL

src/mainboard/siemens/fa_ehl/variants/fa_ehl/Makefile.inc

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-y += mainboard.c

src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb

@@ -0,0 +1,250 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_ALL
+	}"
+
+	# USB related UPDs
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# UNUSED
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# UNUSED
+
+	# Skip the CPU replacement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# PCIe root ports related UPDs
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[6]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
+
+	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+
+	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"
+
+	# Storage (SDCARD/EMMC) related UPDs
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	register "SerialIoUartDmaEnable" = "{
+		[PchSerialIoIndexUART0] = 1,
+		[PchSerialIoIndexUART1] = 1,
+		[PchSerialIoIndexUART2] = 1,
+	}"
+
+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+	register "PseDmaOwn[0]" = "Host_Owned"
+	register "PseDmaOwn[1]" = "Host_Owned"
+	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
+
+	register "common_soc_config" = "{
+		.i2c[1] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1e1,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1df,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+	}"
+
+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+	# Disable L1 prefetcher for real-time demands
+	register "L1_prefetcher_disable" = "true"
+
+	device domain 0 on
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+
+		device pci 14.0 on	end # USB3.1 xHCI
+
+		device pci 15.0 on	end # I2C0
+		device pci 15.1 on	    # I2C1
+			# Enable external RTC chip
+			chip drivers/i2c/rv3028c7
+				register "bus_speed" = "I2C_SPEED_STANDARD"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
+				register "cap_charge" = "CHARGE_OFF"
+				device i2c 0x52 on end  # RTC RV3028-C7
+			end
+		end
+		device pci 15.2 on	    # I2C2
+		# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 15.3 on	end # I2C3
+
+		device pci 16.0 hidden	end # Management Engine Interface 1
+
+		device pci 19.0 on	end # I2C4
+		device pci 19.1 on	end # I2C5
+		device pci 19.2 on	end # UART2
+
+		device pci 1a.0 on	end # eMMC
+		device pci 1a.1 on	end # SD
+
+		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
+
+		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
+		device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 0 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+		device pci 1d.2 on	    # Intel PSE Time-Sensitive Networking GbE 1
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1e.0 on	end # UART0
+		device pci 1e.1 on	end # UART1
+		device pci 1e.4 on	    # PCH Time-Sensitive Networking GbE
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1f.0 on	    # eSPI Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.2 hidden	end # Power Management Controller
+		device pci 1f.4	on	end # SMBus
+		device pci 1f.5 on	end # PCH SPI (flash & TPM)
+	end
+end

src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c

@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+	/* Community 0 - GpioGroup GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),		/* PMC_VRALERT_N */
+	PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4),		/* ESPI_ALERT0_N */
+	PAD_NC(GPP_B4, NONE),				/* Not connected */
+	PAD_NC(GPP_B9, NONE),				/* Not connected */
+	PAD_NC(GPP_B10, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1),		/* PMC_ALERT_N */
+	PAD_NC(GPP_B14, NONE),				/* Not connected */
+	PAD_NC(GPP_B15, NONE),				/* Not connected */
+	PAD_NC(GPP_B18, NONE),				/* Not connected */
+	PAD_NC(GPP_B19, NONE),				/* Not connected */
+	PAD_NC(GPP_B23, NONE),				/* Not connected */
+
+	/* Community 0 - GpioGroup GPP_T */
+	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),		/* PSE_GBE0_INT */
+	PAD_CFG_GPO(GPP_T5, 1, DEEP),			/* PSE_GBE0_RST_N */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),		/* PSE_GBE0_AUXTS */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),		/* PSE_GBE0_PPS */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2),		/* SIO_UART0_RXD */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
+
+	/* Community 0 - GpioGroup GPP_G */
+	PAD_NC(GPP_G8, NONE),				/* Not connected */
+	PAD_NC(GPP_G9, NONE),				/* Not connected */
+	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
+
+	/* Community 1 - GpioGroup GPP_V */
+	PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),		/* EMMC_CMD */
+	PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),		/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),		/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),		/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),		/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),		/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),		/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),		/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),		/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),		/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),		/* EMMC_CLK */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
+
+	/* Community 1 - GpioGroup GPP_H */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),		/* PSE_GBE1_INT */
+	PAD_CFG_GPO(GPP_H1, 1, DEEP),			/* PSE_GBE1_RST_N */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
+
+	/* Community 1 - GpioGroup GPP_D */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),		/* PCIE_CLKREQ0_N */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),		/* PCIE_CLKREQ1_N */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),		/* PCIE_CLKREQ2_N */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),		/* PCIE_CLKREQ3_N */
+
+	/* Community 1 - GpioGroup GPP_U */
+	PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),		/* GBE_INT */
+	PAD_CFG_GPO(GPP_U1, 1, DEEP),			/* GBE_RST_N */
+	PAD_NC(GPP_U12, NONE),				/* Not connected */
+	PAD_NC(GPP_U13, NONE),				/* Not connected */
+	PAD_NC(GPP_U16, NONE),				/* Not connected */
+	PAD_NC(GPP_U17, NONE),				/* Not connected */
+	PAD_NC(GPP_U18, NONE),				/* Not connected */
+
+	/* Community 2 - GpioGroup DSW */
+	PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),		/* ACPRESENT */
+	PAD_NC(GPD9, NONE),				/* Not connected */
+	PAD_NC(GPD11, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_S */
+	PAD_NC(GPP_S0, NONE),				/* Not connected */
+	PAD_NC(GPP_S1, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCTL */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
+
+	/* Community 4 - GpioGroup GPP_C */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
+	PAD_NC(GPP_C8, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* GBE_MDIO */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* GBE_MDC */
+
+	/* Community 4 - GpioGroup GPP_F */
+	PAD_NC(GPP_F1, NONE),				/* Not connected */
+	PAD_NC(GPP_F3, NONE),				/* Not connected */
+	PAD_NC(GPP_F8, NONE),				/* Not connected */
+	PAD_NC(GPP_F11, NONE),				/* Not connected */
+	PAD_NC(GPP_F12, NONE),				/* Not connected */
+	PAD_NC(GPP_F13, NONE),				/* Not connected */
+	PAD_NC(GPP_F14, NONE),				/* Not connected */
+	PAD_NC(GPP_F15, NONE),				/* Not connected */
+	PAD_NC(GPP_F16, NONE),				/* Not connected */
+	PAD_NC(GPP_F17, NONE),				/* Not connected */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),			/* LED_BIOS_DONE */
+
+	/* Community 4 - GpioGroup GPP_E */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),		/* SATA_LED_N */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),		/* M.2_SSD_SATA_DEVSLP_1 */
+	PAD_NC(GPP_E15, NONE),				/* Not connected */
+	PAD_NC(GPP_E16, NONE),				/* Not connected */
+	PAD_NC(GPP_E18, NONE),				/* Not connected */
+	PAD_NC(GPP_E19, NONE),				/* Not connected */
+	PAD_NC(GPP_E23, NONE),				/* Not connected */
+
+	/* Community 5 - GpioGroup GPP_R */
+	PAD_NC(GPP_R1, NONE),				/* Not connected */
+	PAD_NC(GPP_R3, NONE),				/* Not connected */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}

src/mainboard/siemens/fa_ehl/variants/fa_ehl/mainboard.c

@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+#define HOSTCTRL2		0x3E
+#define  HOSTCTRL2_PRESET	(1 << 15)
+#define SD_CAP_BYP		0x810
+#define  SD_CAP_BYP_EN		0x5A
+#define SD_CAP_BYP_REG1		0x814
+#define  SD_CAP_BYP_SDR50	(1 << 13)
+#define  SD_CAP_BYP_SDR104	(1 << 14)
+#define  SD_CAP_BYP_DDR50	(1 << 15)
+
+void variant_mainboard_final(void)
+{
+	struct device *dev;
+
+	/* PIR8 register mapping for PCIe root ports
+	   INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
+	pcr_write16(PID_ITSS, 0x3150, 0x1032);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
+
+	/* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to
+	   layout limitations. */
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	if (dev) {
+		uint32_t reg;
+		uint16_t reg16;
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (!res)
+			return;
+		write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN);
+		reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0));
+		/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+		reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50);
+		reg |= SD_CAP_BYP_DDR50;
+		write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg);
+
+		/* Use preset driver strength from preset value registers. */
+		reg16 = read16(res2mmio(res, HOSTCTRL2, 0));
+		reg16 |= HOSTCTRL2_PRESET;
+		write16(res2mmio(res, HOSTCTRL2, 0), reg16);
+	}
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(GPP_F20, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);

src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg fa_ehl_lpddr4x_memcfg_cfg = {
+
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
+	.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	.rcomp_targets = {60, 40, 30, 20, 30},
+
+	/* LPDDR4x does not allow interleaved memory */
+	.dq_pins_interleaved = 0,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memcfg_config(void)
+{
+	return &fa_ehl_lpddr4x_memcfg_cfg;
+}