mb/google/brox: Fix GPE_EC_WAKE configuration
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration. BUG=b:329026602 TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up using EC generated events like AC connect/disconnect. Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
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@ -74,7 +74,6 @@
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
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#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
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#define EC_ENABLE_SYNC_IRQ /* Enable EC Sync IRQ defined in baseboard/gpio.h */
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#endif /* __BASEBOARD_EC_H__ */
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@ -8,13 +8,13 @@
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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/* EC wake is EC_PCH_INT which is routed to GPP_D0 pin */
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#define GPE_EC_WAKE GPE0_DW1_00
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/* EC wake is EC_PCH_WAKE which is routed to GPP_D1 pin */
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#define GPE_EC_WAKE GPE0_DW1_01
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/* WP signal to PCH */
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#define GPIO_PCH_WP GPP_E8
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/* Used to gate SoC's SLP_S0# signal */
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#define GPIO_SLP_S0_GATE GPP_D17
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/* GPIO IRQ for tight timestamps / wake support */
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/* GPIO IRQ for tight timestamps, MKBP interrupts */
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#define EC_SYNC_IRQ GPP_D0_IRQ
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#endif /* __BASEBOARD_GPIO_H__ */
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