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AGESA binaryPI: Consolidate and fix sleep states

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SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.

Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.

TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.

Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Kyösti Mälkki
2017-08-07 21:42:46 +03:00
parent 1438245334
commit 390ba044dc
64 changed files with 52 additions and 319 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/bettong/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/bettong/dsdt.asl
View File

@@ -38,7 +38,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00660F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/db-ft3b-lc/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

25
src/mainboard/amd/dinar/dsdt.asl
View File

@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSV, Ones) /* Assume nothing */
Name(GPIC, 0x1) /* Assume PIC */
@@ -668,27 +666,8 @@ DefinitionBlock (
}
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

2
src/mainboard/amd/inagua/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/inagua/dsdt.asl
View File

@@ -53,7 +53,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/lamar/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/lamar/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00630F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/olivehill/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/olivehill/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/olivehillplus/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/olivehillplus/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/parmer/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/parmer/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

2
src/mainboard/amd/persimmon/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/persimmon/dsdt.asl
View File

@@ -53,7 +53,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/south_station/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/south_station/dsdt.asl
View File

@@ -53,7 +53,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/amd/thatcher/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/thatcher/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

25
src/mainboard/amd/torpedo/dsdt.asl
View File

@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSV, Ones) /* Assume nothing */
Name(GPIC, 0x1) /* Assume PIC */
@@ -639,27 +637,8 @@ DefinitionBlock (
}
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

2
src/mainboard/amd/union_station/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/amd/union_station/dsdt.asl
View File

@@ -53,7 +53,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/asrock/e350m1/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/asrock/e350m1/dsdt.asl
View File

@@ -49,7 +49,7 @@ DefinitionBlock (
#include "acpi/superio.asl"
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/asrock/imb-a180/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/asrock/imb-a180/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/asus/f2a85-m/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/asus/f2a85-m/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

2
src/mainboard/bap/ode_e20XX/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/bap/ode_e20XX/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/bap/ode_e21XX/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/bap/ode_e21XX/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/biostar/am1ml/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/biostar/am1ml/dsdt.asl
View File

@@ -40,7 +40,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/elmex/pcm205400/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/elmex/pcm205400/dsdt.asl
View File

@@ -53,7 +53,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/gizmosphere/gizmo/dsdt.asl
View File

@@ -48,7 +48,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/gizmosphere/gizmo2/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/hp/abm/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/hp/abm/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl
View File

@@ -41,7 +41,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

2
src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
View File

@@ -47,7 +47,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/lenovo/g505s/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/lenovo/g505s/dsdt.asl
View File

@@ -41,7 +41,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15rl/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

24
src/mainboard/lippert/frontrunner-af/dsdt.asl
View File

@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -791,26 +789,8 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

25
src/mainboard/lippert/toucan-af/dsdt.asl
View File

@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -790,27 +788,8 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

2
src/mainboard/msi/ms7721/acpi/mainboard.asl
View File

@@ -24,8 +24,6 @@
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/msi/ms7721/dsdt.asl
View File

@@ -37,7 +37,7 @@ DefinitionBlock (
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"

2
src/mainboard/pcengines/apu1/acpi/mainboard.asl
View File

@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/pcengines/apu1/dsdt.asl
View File

@@ -48,7 +48,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

2
src/mainboard/pcengines/apu2/acpi/mainboard.asl
View File

@@ -22,8 +22,6 @@ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */

2
src/mainboard/pcengines/apu2/dsdt.asl
View File

@@ -39,7 +39,7 @@ DefinitionBlock (
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"

25
src/mainboard/supermicro/h8qgi/dsdt.asl
View File

@@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -834,27 +832,8 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

25
src/mainboard/supermicro/h8scm/dsdt.asl
View File

@@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -834,27 +832,8 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

25
src/mainboard/tyan/s8226/dsdt.asl
View File

@@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -834,27 +832,8 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})

36
src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl
View File

@@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */

33
src/southbridge/amd/cimx/sb800/acpi/sleepstates.asl
View File

@@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */

20
src/southbridge/amd/pi/hudson/acpi/sleepstates.asl → src/southbridge/amd/common/acpi/sleepstates.asl
View File

@@ -14,25 +14,27 @@
* GNU General Public License for more details.
*/
/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name (SSFG, 0x0D)
#else
Name (SSFG, 0x09)
#endif
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
If (And(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
If (And(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
If (LAnd(SSFG, 0x04)) {
If (And(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
#endif
If (LAnd(SSFG, 0x08)) {
If (And(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */