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intel cache-as-ram: Unify stack setup

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No need to have %ebx reserved here.

Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17357
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-11-08 12:13:15 +02:00
parent a4ffe9dda0
commit 39915bc290
5 changed files with 16 additions and 35 deletions
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5
src/cpu/intel/haswell/cache_as_ram.inc
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@@ -177,7 +177,7 @@ before_romstage:
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
movl %eax, %ebx
movl %eax, %esp
post_code(0x30)
@@ -225,9 +225,6 @@ before_romstage:
post_code(0x38)
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
/* Get number of MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx