soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this to 1 is needed to enable HDA audio link. Same exact situation as with Alder Lake in CL 71715. Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
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@@ -247,6 +247,7 @@ struct soc_intel_meteorlake_config {
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uint16_t sata_ports_dito_val[8];
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/* Audio related */
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uint8_t pch_hda_audio_link_hda_enable;
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uint8_t pch_hda_dsp_enable;
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bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
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@@ -288,17 +288,11 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
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m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
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m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
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m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
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for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
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m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
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/*
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* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
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* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
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* configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
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* configuration for audio pads.
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*/
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m_cfg->PchHdaAudioLinkHdaEnable = 0;
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memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
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memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
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memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
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