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soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree

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The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.

Same exact situation as with Alder Lake in CL 71715.

Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Michał Kopeć
2024-05-28 12:35:08 +02:00
committed by Felix Held
parent a79af4c7fd
commit 3a26aec8bd
2 changed files with 2 additions and 7 deletions
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1
src/soc/intel/meteorlake/chip.h
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@@ -247,6 +247,7 @@ struct soc_intel_meteorlake_config {
uint16_t sata_ports_dito_val[8]; uint16_t sata_ports_dito_val[8];
/* Audio related */ /* Audio related */
uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable; uint8_t pch_hda_dsp_enable;
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS]; bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];

8
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@@ -288,17 +288,11 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
/*
* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
* configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
* configuration for audio pads.
*/
m_cfg->PchHdaAudioLinkHdaEnable = 0;
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));