mb/system76/adl: Convert gaze17 to variants

Change-Id: I086a13a293986bb82692c08aae8fd675083ff16b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-03-07 11:39:23 -07:00
committed by Jeremy Soller
parent 05bdd8036d
commit 3a8ee1a86e
36 changed files with 230 additions and 514 deletions

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@@ -24,21 +24,36 @@ config BOARD_SYSTEM76_ADL_COMMON
select SYSTEM_TYPE_LAPTOP
config BOARD_SYSTEM76_DARP8
def_bool n
select BOARD_SYSTEM76_ADL_COMMON
select EC_SYSTEM76_EC_COLOR_KEYBOARD
config BOARD_SYSTEM76_GALP6
def_bool n
select BOARD_SYSTEM76_ADL_COMMON
config BOARD_SYSTEM76_GAZE17_3050
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select TPM_RDRESP_NEED_DELAY
config BOARD_SYSTEM76_GAZE17_3060_B
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select MAINBOARD_USES_IFD_GBE_REGION
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select TPM_RDRESP_NEED_DELAY
config BOARD_SYSTEM76_LEMP11
def_bool n
select BOARD_SYSTEM76_ADL_COMMON
select HAVE_SPD_IN_CBFS
config BOARD_SYSTEM76_ORYP9
def_bool n
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_TAS5825M
@@ -46,7 +61,6 @@ config BOARD_SYSTEM76_ORYP9
select EC_SYSTEM76_EC_DGPU
config BOARD_SYSTEM76_ORYP10
def_bool n
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
@@ -60,6 +74,8 @@ config MAINBOARD_DIR
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -70,6 +86,8 @@ config OVERRIDE_DEVICETREE
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -77,12 +95,15 @@ config MAINBOARD_PART_NUMBER
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
default "Galago Pro" if BOARD_SYSTEM76_GALP6
default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10

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@@ -4,6 +4,12 @@ config BOARD_SYSTEM76_DARP8
config BOARD_SYSTEM76_GALP6
bool "galp6"
config BOARD_SYSTEM76_GAZE17_3050
bool "gaze17 3050"
config BOARD_SYSTEM76_GAZE17_3060_B
bool "gaze17 3060-b"
config BOARD_SYSTEM76_LEMP11
bool "lemp11"

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@@ -1,3 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

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@@ -1,5 +1,8 @@
FLASH 32M {
SI_DESC 4K
#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION
SI_GBE 8K
#endif
SI_ME 4824K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K

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@@ -70,9 +70,8 @@ chip soc/intel/alderlake
device ref heci1 on end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable[1]" = "1" # SSD1
# FIXME: DevSlp breaks S0ix
#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
register "sata_ports_enable[1]" = "1"
register "sata_ports_dev_slp[1]" = "1"
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel

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@@ -0,0 +1,2 @@
Board name: gaze17-3050
Release year: 2022

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@@ -1,16 +1,49 @@
chip soc/intel/alderlake
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
device domain 0 on
subsystemid 0x1558 0x866d inherit
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
device ref pcie5_0 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
@@ -20,6 +53,34 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR,
}"
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 off end
device ref tbt_pcie_rp0 off end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1

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@@ -1,28 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <fsp/util.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
static const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
.ddr_config = {
.dq_pins_interleaved = false,
},
};
static const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
@@ -30,16 +24,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
// Enable audio link
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;

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@@ -0,0 +1,2 @@
Board name: gaze17-3060-b
Release year: 2022

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@@ -1,7 +1,50 @@
chip soc/intel/alderlake
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
device domain 0 on
subsystemid 0x1558 0x867c inherit
device ref pcie5_0 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
@@ -17,7 +60,33 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR,
}"
end
device ref tbt_pcie_rp0 on end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 off end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref tcss_dma0 on end
device ref xhci on
# USB2

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@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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@@ -1,78 +0,0 @@
if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select EC_SYSTEM76_EC_LOCKDOWN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE17_3060_B
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_RDRESP_NEED_DELAY
config MAINBOARD_DIR
default "system76/gaze17"
config VARIANT_DIR
default "3050" if BOARD_SYSTEM76_GAZE17_3050
default "3060" if BOARD_SYSTEM76_GAZE17_3060_B
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Gazelle"
config MAINBOARD_VERSION
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
config CONSOLE_POST
default y
config DIMM_SPD_SIZE
default 512
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
config ONBOARD_VGA_IS_PRIMARY
default y
config POST_DEVICE
default n
config TPM_MEASURED_BOOT
default y
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@@ -1,5 +0,0 @@
config BOARD_SYSTEM76_GAZE17_3050
bool "gaze17 3050"
config BOARD_SYSTEM76_GAZE17_3060_B
bool "gaze17 3060-b"

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@@ -1,13 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c

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@@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0)
{
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

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@@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(DRIVERS_GFX_NVIDIA)
#include <variant/gpio.h>
#endif
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
#if CONFIG(DRIVERS_GFX_NVIDIA)
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#endif
}
}

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@@ -1,46 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < 6, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

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@@ -1,15 +0,0 @@
FLASH 32M {
SI_DESC 4K
#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION
SI_GBE 8K
#endif
SI_ME 4824K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

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@@ -1,8 +0,0 @@
Vendor name: System76
Board name: gaze17
Category: laptop
Release year: 2022
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

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@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <mainboard/gpio.h>
void bootblock_mainboard_early_init(void)
{
mainboard_configure_early_gpios();
}

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@@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Disable

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@@ -1,39 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

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@@ -1,132 +0,0 @@
chip soc/intel/alderlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# ACPI (soc/intel/alderlake/acpi.c)
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/alderlake/fsp_params.c)
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# PM Util (soc/intel/alderlake/pmutil.c)
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
#From CPU EDS(TODO)
device ref system_agent on end
device ref pcie5_0 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref heci1 on end
device ref sata on
register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0E01" # AP/EC command
register "gen3_dec" = "0x00fc0F01" # AP/EC debug
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref pmc hidden end
device ref hda on
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end
device ref smbus on end
device ref fast_spi on end
end
end

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@@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
#include <soc/intel/alderlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

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@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

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@@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/ramstage.h>
#include <smbios.h>
smbios_wakeup_type smbios_system_wakeup_type(void)
{
return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
params->SataPortsSolidStateDrive[1] = 1;
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};