soc/amd/mendocino: Set up SoC-specific XHCI defines
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BUG=b:186792595 TEST=builds Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67938 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -74,6 +74,7 @@ config SOC_AMD_REMBRANDT_BASE
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_XHCI
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI
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15
src/soc/amd/mendocino/include/soc/xhci.h
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15
src/soc/amd/mendocino/include/soc/xhci.h
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@@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_MENDOCINO_XHCI_H
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#define AMD_MENDOCINO_XHCI_H
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#define SOC_XHCI_0 DEV_PTR(xhci_0)
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#define SOC_XHCI_1 DEV_PTR(xhci_1)
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#define SOC_XHCI_2 DEV_PTR(xhci_2)
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#define SOC_XHCI_3 NULL
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#define SOC_XHCI_4 NULL
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#define SOC_XHCI_5 NULL
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#define SOC_XHCI_6 NULL
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#define SOC_XHCI_7 NULL
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#endif /* AMD_MENDOCINO_XHCI_H */
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