soc/intel/xeon_sp/smihandler.c: enable support for spr-sp

For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC
instead of UBOX_DEV_PMON.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -12,6 +12,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp

src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h

@@ -183,4 +183,6 @@
 #define IIO_DFX_TSWCTL0		0x30c
 #define IIO_DFX_LCK_CTL		0x504
 
+pci_devfn_t soc_get_ubox_pmon_dev(void);
+
 #endif /* _SOC_PCI_DEVS_H_ */

src/soc/intel/xeon_sp/cpx/soc_smihandler_util.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pci_devs.h>
+
+pci_devfn_t soc_get_ubox_pmon_dev(void)
+{
+	return UBOX_DEV_PMON;
+}

src/soc/intel/xeon_sp/skx/Makefile.inc

@@ -21,6 +21,7 @@ ramstage-y += cpu.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-y += hob_display.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
 

src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h

@@ -164,4 +164,6 @@
 #define IIO_DFX_TSWCTL0		0x30c
 #define IIO_DFX_LCK_CTL		0x504
 
+pci_devfn_t soc_get_ubox_pmon_dev(void);
+
 #endif /* _SOC_PCI_DEVS_H_ */

src/soc/intel/xeon_sp/skx/soc_smihandler_util.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pci_devs.h>
+
+pci_devfn_t soc_get_ubox_pmon_dev(void)
+{
+	return UBOX_DEV_PMON;
+}

src/soc/intel/xeon_sp/smihandler.c

@@ -57,9 +57,23 @@ void smihandler_soc_at_finalize(void)
 {
 	/* SMM_FEATURE_CONTROL can only be written within SMM. */
 	printk(BIOS_DEBUG, "Lock SMM_FEATURE_CONTROL\n");
-	const pci_devfn_t dev = UBOX_DEV_PMON;
-	pci_or_config32(dev, SMM_FEATURE_CONTROL,
-			SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK);
+	pci_devfn_t pcie_offset = soc_get_ubox_pmon_dev();
+	if (!pcie_offset) {
+		printk(BIOS_ERR, "UBOX PMON is not found, cannot lock SMM_FEATURE_CONTROL!\n");
+		return;
+	}
+
+	u32 val;
+	val = pci_s_read_config32(pcie_offset, SMM_FEATURE_CONTROL);
+	val |= (SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK);
+	pci_s_write_config32(pcie_offset, SMM_FEATURE_CONTROL, val);
+}
+
+/*
+ * This is the generic entry for SOC SMIs
+ */
+void cpu_smi_handler(void)
+{
 
 }
 

src/soc/intel/xeon_sp/spr/Makefile.inc

@@ -16,6 +16,7 @@ ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.
 ramstage-y += crashlog.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
 
 endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP

src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h

@@ -4,6 +4,7 @@
 #define _SOC_PCI_DEVS_H_
 
 #include <device/pci_def.h>
+#include <device/pci_type.h>
 #include <types.h>
 
 #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
@@ -230,4 +231,6 @@
 #define BIOS_CRASHLOG_CTL 0x158
 #define CRASHLOG_CTL_DIS BIT(2)
 
+pci_devfn_t soc_get_ubox_pmon_dev(void);
+
 #endif /* _SOC_PCI_DEVS_H_ */

src/soc/intel/xeon_sp/spr/soc_smihandler_util.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include <device/pci.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+
+pci_devfn_t soc_get_ubox_pmon_dev(void)
+{
+	msr_t msr = rdmsr(MSR_CPU_BUSNO);
+	u16 bus;
+
+	if (msr.hi & BUSNO_VALID)
+		bus = msr.lo & 0xff;
+	else
+		return 0;
+
+	return PCI_DEV(bus, UBOX_DECS_DEV, UBOX_URACU_FUNC);
+}