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Apply TCSS recommendations from 617016

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Change-Id: Ia30fa057f3f03e8d7e82d067e09ea85a7bab3385
This commit is contained in:
Jeremy Soller
2020-11-24 14:40:41 -07:00
parent 13338f9ae2
commit 3d37711899
4 changed files with 12 additions and 8 deletions
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8
src/mainboard/system76/galp5/gpio.h
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@@ -265,10 +265,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
// NC
PAD_NC(GPP_E17, NONE),
// GPP_E18_TBT_LSX0_TXD
_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
// GPP_E19_TBT_LSX0_RXD
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
// GPP_E18_TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E18, NONE),
// GPP_E19_TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E19, NONE),
// NC
PAD_NC(GPP_E20, NONE),
// NC

2
src/mainboard/system76/galp5/ramstage.c
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@@ -11,6 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[5] = 1; // J_TYPEC2
params->UsbTcPortEn = 1;
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

8
src/mainboard/system76/lemp10/gpio.h
View File

@@ -258,10 +258,10 @@ static const struct pad_config gpio_table[] = {
_PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000),
// NC
PAD_NC(GPP_E17, NONE),
// TBT_LSX0_TXD
_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
// TBT_LSX0_RXD
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
// TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E18, NONE),
// TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
PAD_NC(GPP_E19, NONE),
// SWI#
_PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000),
// GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V)

2
src/mainboard/system76/lemp10/ramstage.c
View File

@@ -11,6 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
// IOM config
params->PchUsbOverCurrentEnable = 0;
params->PortResetMessageEnable[2] = 1; // J_TYPEC1
params->UsbTcPortEn = 1;
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}